| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wl-hse-clock.yaml | 4 description: STM32WL HSE Clock
6 compatible: "st,stm32wl-hse-clock"
11 hse-tcxo:
14 When set, TCXO is selected as external source clock for HSE.
15 Otherwise, external crystal is selected as HSE source clock.
17 hse-div2:
20 When set HSE output clock is divided by 2.
|
| D | st,stm32-hse-clock.yaml | 4 description: STM32 HSE Clock
6 compatible: "st,stm32-hse-clock"
11 hse-bypass:
14 HSE crystal oscillator bypass
20 HSE clock security system enabled
21 Set the property to enable the clock security system (CSS) for the HSE clock.
23 If a failure is detected on the HSE clock, the HSE oscillator is automatically disabled,
|
| D | st,stm32wba-hse-clock.yaml | 4 description: STM32WBA HSE Clock
6 compatible: "st,stm32wba-hse-clock"
11 hse-div2:
14 When set HSE output clock is divided by 2.
|
| D | wch,ch32v00x-hse-clock.yaml | 4 description: WCH CH32V00x HSE Clock
6 compatible: "wch,ch32v00x-hse-clock"
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/boards/ |
| D | wl_pll_48_hse_32.overlay | 10 * It applies to the stm32wl where the hse prescaler is 2 and by-passed
14 hse-tcxo;
15 hse-div2;
|
| D | clear_clocks.overlay | 14 /delete-property/ hse-bypass;
16 /delete-property/ hse-tcxo;
17 /delete-property/ hse-div2;
|
| D | wl_32_hse.overlay | 10 * It applies to the stm32wl where the hse prescaler is 1 and by-passed
14 hse-tcxo;
|
| D | hse_css.overlay | 8 * Warning: This overlay assumes the HSE clock has already been enabled,
|
| /Zephyr-latest/dts/bindings/phy/ |
| D | st,stm32u5-otghs-phy.yaml | 7 with USB HS PHY IP and a configurable HSE clock source.
22 /* HSE */
26 /* HSE/2 */
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/ |
| D | wl_i2c1_sysclk_lptim1_lsi.overlay | 13 /delete-property/ hse-bypass;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
50 hse-tcxo;
|
| D | wl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay | 13 /delete-property/ hse-bypass;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
50 hse-tcxo;
|
| D | wb_i2c1_sysclk_lptim1_lsi.overlay | 13 /delete-property/ hse-bypass;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
|
| D | wb_i2c1_hsi_lptim1_lse.overlay | 13 /delete-property/ hse-bypass;
15 /delete-property/ hse-tcxo;
16 /delete-property/ hse-div2;
|
| D | f4_i2s2_pll.overlay | 13 /delete-property/ hse-bypass;
52 hse-bypass;
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/ |
| D | testcase.yaml | 21 # Build only as HSE not implemened on available boards
25 # Build only as HSE not implemened on available boards
29 # Build only as HSE not implemened on available boards
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h7_core/src/ |
| D | test_stm32_clock_configuration.c | 35 "Expected sysclk src: HSE (0x%x). Actual: 0x%x", in ZTEST()
62 "Expected PLL src: HSE (%d). Actual PLL src: %d", in ZTEST()
85 zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS is not enabled"); in ZTEST()
87 zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSHSEON), "HSE CSS unexpectedly enabled"); in ZTEST()
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/ |
| D | hse_16.overlay | 13 * Warning: HSE is not implemented on available boards, hence:
20 hse-bypass;
|
| D | pll_hse_160.overlay | 13 * Warning: HSE is not implemented on available boards, hence:
20 hse-bypass;
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/ |
| D | hse25.overlay | 14 * Warning: HSE frequency differs on available boards, hence:
20 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
|
| D | pll_hse25_100.overlay | 14 * Warning: HSE frequency differs on available boards, hence:
19 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
|
| D | pll_hse25_240.overlay | 14 * Warning: HSE frequency differs on available boards, hence:
19 hse-bypass; /* X3 is a 25MHz oscillator on PH0 */
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_core/src/ |
| D | test_stm32_clock_configuration.c | 44 "Expected sysclk src: HSE (0x%x). Actual: 0x%x", in ZTEST()
71 "Expected PLL src: HSE (%d). Actual PLL src: %d", in ZTEST()
114 zassert_true(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS is not enabled"); in ZTEST()
116 zassert_false(READ_BIT(RCC->CR, RCC_CR_CSSON), "HSE CSS unexpectedly enabled"); in ZTEST()
|
| /Zephyr-latest/boards/arduino/opta/ |
| D | board_gpio_init.c | 13 /* The external oscillator that drives the HSE clock should be enabled in board_gpio_init()
18 * Note that the HSE should be turned on by the M7 only because M4 in board_gpio_init()
|
| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32f1.c | 72 * PLLXPTRE (depends on PLL source HSE) in config_pll_sysclock()
73 * HSE/2 used as PLL source in config_pll_sysclock()
79 * PLLXPTRE (depends on PLL source HSE) in config_pll_sysclock()
80 * HSE used as direct PLL source in config_pll_sysclock()
|
| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/src/ |
| D | test_stm32_clock_configuration.c | 35 "Expected sysclk src: HSE. Actual sysclk src: %d", in ZTEST()
57 "Expected PLL src: HSE. Actual PLL src: %d", in ZTEST()
|
