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/Zephyr-latest/drivers/clock_control/
Dclock_control_npcm.c28 /* High Frequency Clock Generator (HFCG) registers */
29 /* 0x000: HFCG Control */
32 /* 0x002: HFCG M Low Byte Value */
35 /* 0x004: HFCG M High Byte Value */
38 /* 0x006: HFCG N Value */
41 /* 0x008: HFCG Prescaler */
44 /* 0x010: HFCG Bus Clock Dividers */
47 /* 0x012: HFCG Bus Clock Dividers */
50 /* 0x014: HFCG Bus Clock Dividers */
53 /* 0x01d: HFCG Bus Clock Dividers */
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
36 Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
Dnuvoton,npcx-pcc.yaml8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
33 Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
/Zephyr-latest/soc/nuvoton/npcx/common/reg/
Dreg_def.h57 /* High Frequency Clock Generator (HFCG) registers */
58 /* 0x000: HFCG Control */
61 /* 0x002: HFCG M Low Byte Value */
64 /* 0x004: HFCG M High Byte Value */
67 /* 0x006: HFCG N Value */
70 /* 0x008: HFCG Prescaler */
73 /* 0x010: HFCG Bus Clock Dividers */
76 /* 0x012: HFCG Bus Clock Dividers */
79 /* 0x014: HFCG Bus Clock Dividers */
82 /* 0x01d: HFCG Bus Clock Dividers */