Searched full:gmii (Results 1 – 10 of 10) sorted by relevance
83 internal FIFO on to the internal MII/GMII interface, passing through85 This mode requires the MII/GMII Rx clock input signal to function
161 /* GMII Address */163 /* GMII Data */285 /* GMII Address */296 /* GMII Data */
975 /* 1. Program the GMII Address Register (offset 0x10) for controlling the in eth_cyclonev_probe()976 * management cycles for theexternal PHY. Bits[15:11] of the GMII Address in eth_cyclonev_probe()980 * 2. Read the 16-bit data of the GMII Data Register from the PHY for link up, in eth_cyclonev_probe()982 * address value in bits[15:11] of the GMII Address Register. in eth_cyclonev_probe()
255 * [11] Use TBI instead of the GMII/MII interface
966 /* [11] enable TBI instead of GMII/MII */ in eth_xlnx_gem_set_initial_nwcfg()
38 - "gmii"
40 soft PCS is connected to XGMAC through GMII. make sure the phy-connection-type is41 selected as gmii when 2500Mbit/s speed is selected.
282 bled instead of the GMII/MII interface.
103 - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
106 - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
