Searched full:fifo2 (Results 1 – 8 of 8) sorted by relevance
| /Zephyr-latest/tests/kernel/fifo/fifo_usage/src/ |
| D | main.c | 21 * Test Thread enters an item into fifo2, starts a Child Thread and
23 * will extract an item from fifo2 once the item is there and enter
28 * Tests the ISR interfaces. Test thread puts items into fifo2 and gives
29 * control to the Child thread. Child thread gets items from fifo2 and then
47 static K_FIFO_DEFINE(fifo2);
109 /* Get items from fifo2 */ in thread_entry_fn_dual()
120 /* Get items from fifo2 */ in thread_entry_fn_isr()
176 * @details test Thread enters an item into fifo2, starts a Child Thread and
178 * will extract an item from fifo2 once the item is there and enter
189 thread_entry_fn_dual, &fifo1, &fifo2, NULL, in ZTEST()
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| /Zephyr-latest/tests/benchmarks/sys_kernel/src/ |
| D | mwfifo.c | 13 struct k_fifo fifo2; variable
26 k_fifo_init(&fifo2); in fifo_test_init()
54 k_fifo_put(&fifo2, element); in fifo_thread1()
83 pelement = k_fifo_get(&fifo2, K_FOREVER); in fifo_thread2()
116 while ((pelement = k_fifo_get(&fifo2, K_NO_WAIT)) == NULL) { in fifo_thread3()
236 pelement = k_fifo_get(&fifo2, K_FOREVER); in fifo_test()
240 pelement = k_fifo_get(&fifo2, K_FOREVER); in fifo_test()
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | ite,it8xxx2-i2c.yaml | 15 FIFO2 supports channel B.
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| /Zephyr-latest/drivers/i2c/ |
| D | Kconfig.it8xxx2 | 24 FIFO1 supports channel A. FIFO2 supports channel B.
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| D | i2c_ite_it8xxx2.c | 704 * FIFO2 only supports one channel of B or C. If the FIFO of in fifo_mode_allowed()
1141 /* Select channel B in FIFO2. */ in i2c_it8xxx2_init()
1144 /* Select channel C in FIFO2. */ in i2c_it8xxx2_init()
1266 * This issue occurs when FIFO2 is enabled on channel C. The problem
1267 * arises because FIFO2 is shared between channel B and channel C.
1268 * FIFO2 will be disabled when data access is completed, at which point
1269 * FIFO2 is set to the default configuration for channel B.
1270 * The byte counter of FIFO2 may be affected by channel B. There is a chance
1271 * that channel C may encounter wrong register being written due to FIFO2
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| /Zephyr-latest/tests/kernel/obj_core/obj_core/src/ |
| D | main.c | 24 static struct k_fifo fifo2; variable
224 k_fifo_init(&fifo2); in ZTEST()
226 K_OBJ_CORE(&fifo1), K_OBJ_CORE(&fifo2)); in ZTEST()
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| /Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_shi_ite.c | 194 /* CPU Tx FIFO1 and FIFO2 access */ in shi_ite_response_host_data()
409 * bit4 : Rx FIFO2 will not be overwrited once it's full. in shi_ite_init_registers()
411 * bit0 : Rx FIFO1/FIFO2 will reset after each CS_N goes high. in shi_ite_init_registers()
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| /Zephyr-latest/dts/riscv/ite/ |
| D | it81xx2.dtsi | 384 fifo-enable; /* FIFO2 */
401 /delete-property/ fifo-enable; /* FIFO2 */
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