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/Zephyr-latest/boards/nordic/nrf54h20dk/
Dnrf54h20dk_nrf54h20-memory_map.dtsi12 reg = <0x2f010000 DT_SIZE_K(4)>;
20 reg = <0x0 DT_SIZE_K(2)>;
24 reg = <0x800 DT_SIZE_K(2)>;
30 reg = <0x2f011000 DT_SIZE_K(260)>;
38 reg = <0x0 DT_SIZE_K(2)>;
42 reg = <0x800 DT_SIZE_K(2)>;
46 reg = <0x1000 DT_SIZE_K(256)>;
52 reg = <0x2f0be000 DT_SIZE_K(4)>;
61 reg = <0x0 DT_SIZE_K(4)>;
67 reg = <0x2f0bf000 DT_SIZE_K(4)>;
[all …]
/Zephyr-latest/boards/nordic/nrf9280pdk/
Dnrf9280pdk_nrf9280-memory_map.dtsi16 reg = <0x2f011000 DT_SIZE_K(4)>;
24 reg = <0x0 DT_SIZE_K(2)>;
28 reg = <0x800 DT_SIZE_K(2)>;
34 reg = <0x2f012000 DT_SIZE_K(516)>;
42 reg = <0x0 DT_SIZE_K(2)>;
46 reg = <0x800 DT_SIZE_K(2)>;
50 reg = <0x1000 DT_SIZE_K(512)>;
56 reg = <0x2f0cf000 DT_SIZE_K(4)>;
65 reg = <0x0 DT_SIZE_K(2)>;
69 reg = <0x800 DT_SIZE_K(2)>;
[all …]
/Zephyr-latest/dts/common/espressif/
Dpartitions_0x0_amp_16M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(6080)>;
26 reg = <0x610000 DT_SIZE_K(1920)>;
31 reg = <0x7F0000 DT_SIZE_K(6080)>;
36 reg = <0xDE0000 DT_SIZE_K(1920)>;
41 reg = <0xFC0000 DT_SIZE_K(128)>;
46 reg = <0xFE0000 DT_SIZE_K(64)>;
51 reg = <0xFF0000 DT_SIZE_K(4)>;
Dpartitions_0x0_amp_2M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(576)>;
26 reg = <0xB0000 DT_SIZE_K(256)>;
31 reg = <0xF0000 DT_SIZE_K(576)>;
36 reg = <0x1a0000 DT_SIZE_K(256)>;
41 reg = <0x1C0000 DT_SIZE_K(128)>;
46 reg = <0x1E0000 DT_SIZE_K(64)>;
51 reg = <0x1F0000 DT_SIZE_K(4)>;
Dpartitions_0x0_amp_32M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(12352)>;
26 reg = <0xC30000 DT_SIZE_K(3840)>;
31 reg = <0xFF0000 DT_SIZE_K(12352)>;
36 reg = <0x1C00000 DT_SIZE_K(3840)>;
41 reg = <0x1FC0000 DT_SIZE_K(128)>;
46 reg = <0x1FE0000 DT_SIZE_K(64)>;
51 reg = <0x1FF0000 DT_SIZE_K(4)>;
Dpartitions_0x0_amp_4M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(1344)>;
26 reg = <0x170000 DT_SIZE_K(512)>;
31 reg = <0x1F0000 DT_SIZE_K(1344)>;
36 reg = <0x340000 DT_SIZE_K(512)>;
41 reg = <0x3C0000 DT_SIZE_K(128)>;
46 reg = <0x3E0000 DT_SIZE_K(64)>;
51 reg = <0x3F0000 DT_SIZE_K(4)>;
Dpartitions_0x0_amp_8M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(3136)>;
26 reg = <0x330000 DT_SIZE_K(768)>;
31 reg = <0x3F0000 DT_SIZE_K(3136)>;
36 reg = <0x700000 DT_SIZE_K(768)>;
41 reg = <0x7C0000 DT_SIZE_K(128)>;
46 reg = <0x7E0000 DT_SIZE_K(64)>;
51 reg = <0x7F0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_amp_16M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(6080)>;
26 reg = <0x610000 DT_SIZE_K(1920)>;
31 reg = <0x7F0000 DT_SIZE_K(6080)>;
36 reg = <0xDE0000 DT_SIZE_K(1920)>;
41 reg = <0xFC0000 DT_SIZE_K(128)>;
46 reg = <0xFE0000 DT_SIZE_K(64)>;
51 reg = <0xFF0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_amp_2M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(576)>;
26 reg = <0xB0000 DT_SIZE_K(256)>;
31 reg = <0xF0000 DT_SIZE_K(576)>;
36 reg = <0x180000 DT_SIZE_K(256)>;
41 reg = <0x1C0000 DT_SIZE_K(128)>;
46 reg = <0x1E0000 DT_SIZE_K(64)>;
51 reg = <0x1F0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_amp_32M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(12352)>;
26 reg = <0xC24000 DT_SIZE_K(3840)>;
31 reg = <0xFF0000 DT_SIZE_K(12352)>;
36 reg = <0x1C00000 DT_SIZE_K(3840)>;
41 reg = <0x1FC0000 DT_SIZE_K(128)>;
46 reg = <0x1FE0000 DT_SIZE_K(64)>;
51 reg = <0x1FF0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_amp_4M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(1344)>;
26 reg = <0x170000 DT_SIZE_K(512)>;
31 reg = <0x1F0000 DT_SIZE_K(1344)>;
36 reg = <0x340000 DT_SIZE_K(512)>;
41 reg = <0x3C0000 DT_SIZE_K(128)>;
46 reg = <0x3E0000 DT_SIZE_K(64)>;
51 reg = <0x3F0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_amp_8M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(3136)>;
26 reg = <0x330000 DT_SIZE_K(768)>;
31 reg = <0x3F0000 DT_SIZE_K(3136)>;
36 reg = <0x700000 DT_SIZE_K(768)>;
41 reg = <0x7C0000 DT_SIZE_K(128)>;
46 reg = <0x7E0000 DT_SIZE_K(64)>;
51 reg = <0x7F0000 DT_SIZE_K(4)>;
Dpartitions_0x0_default_16M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(8000)>;
26 reg = <0x7F0000 DT_SIZE_K(8000)>;
31 reg = <0xFC0000 DT_SIZE_K(128)>;
36 reg = <0xFE0000 DT_SIZE_K(64)>;
41 reg = <0xFF0000 DT_SIZE_K(4)>;
Dpartitions_0x0_default_2M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(832)>;
26 reg = <0xF0000 DT_SIZE_K(832)>;
31 reg = <0x1C0000 DT_SIZE_K(128)>;
36 reg = <0x1E0000 DT_SIZE_K(64)>;
41 reg = <0x1F0000 DT_SIZE_K(4)>;
Dpartitions_0x0_default_32M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(16192)>;
26 reg = <0xFF0000 DT_SIZE_K(16192)>;
31 reg = <0x1FC0000 DT_SIZE_K(128)>;
36 reg = <0x1FE0000 DT_SIZE_K(64)>;
41 reg = <0x1FF0000 DT_SIZE_K(4)>;
Dpartitions_0x0_default_4M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(1856)>;
26 reg = <0x1F0000 DT_SIZE_K(1856)>;
31 reg = <0x3C0000 DT_SIZE_K(128)>;
36 reg = <0x3E0000 DT_SIZE_K(64)>;
41 reg = <0x3F0000 DT_SIZE_K(4)>;
Dpartitions_0x0_default_8M.dtsi16 reg = <0x0 DT_SIZE_K(64)>;
21 reg = <0x20000 DT_SIZE_K(3904)>;
26 reg = <0x3F0000 DT_SIZE_K(3904)>;
31 reg = <0x7C0000 DT_SIZE_K(128)>;
36 reg = <0x7E0000 DT_SIZE_K(64)>;
41 reg = <0x7F0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_default_16M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(8000)>;
26 reg = <0x7F0000 DT_SIZE_K(8000)>;
31 reg = <0xFC0000 DT_SIZE_K(128)>;
36 reg = <0xFE0000 DT_SIZE_K(64)>;
41 reg = <0xFF0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_default_2M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(832)>;
26 reg = <0xF0000 DT_SIZE_K(832)>;
31 reg = <0x1C0000 DT_SIZE_K(128)>;
36 reg = <0x1E0000 DT_SIZE_K(64)>;
41 reg = <0x1F0000 DT_SIZE_K(4)>;
Dpartitions_0x1000_default_32M.dtsi16 reg = <0x1000 DT_SIZE_K(60)>;
21 reg = <0x20000 DT_SIZE_K(16192)>;
26 reg = <0xFF0000 DT_SIZE_K(16192)>;
31 reg = <0x1FC0000 DT_SIZE_K(128)>;
36 reg = <0x1FE0000 DT_SIZE_K(64)>;
41 reg = <0x1FF0000 DT_SIZE_K(4)>;
/Zephyr-latest/boards/nordic/nrf54l15dk/
Dnrf54l15dk_nrf54l05_cpuapp.dts24 reg = <0x20000000 DT_SIZE_K(96)>;
25 ranges = <0x0 0x20000000 DT_SIZE_K(96)>;
29 reg = <0x0 DT_SIZE_K(500)>;
40 reg = <0x0 DT_SIZE_K(64)>;
44 reg = <0x10000 DT_SIZE_K(100)>;
48 reg = <0x29000 DT_SIZE_K(100)>;
52 reg = <0x42000 DT_SIZE_K(100)>;
56 reg = <0x5b000 DT_SIZE_K(100)>;
60 reg = <0x74000 DT_SIZE_K(36)>;
Dnrf54l15dk_nrf54l10_cpuapp.dts24 reg = <0x20000000 DT_SIZE_K(192)>;
25 ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
29 reg = <0x0 DT_SIZE_K(1022)>;
40 reg = <0x0 DT_SIZE_K(64)>;
44 reg = <0x10000 DT_SIZE_K(230)>;
48 reg = <0x49800 DT_SIZE_K(230)>;
52 reg = <0x83000 DT_SIZE_K(230)>;
56 reg = <0xbc800 DT_SIZE_K(230)>;
60 reg = <0xf6000 DT_SIZE_K(38)>;
/Zephyr-latest/dts/common/nordic/
Dnrf54l05.dtsi10 reg = <0x20000000 DT_SIZE_K(72)>;
11 ranges = <0x0 0x20000000 DT_SIZE_K(72)>;
19 reg = <0x20012000 DT_SIZE_K(24)>;
22 ranges = <0x0 0x20012000 DT_SIZE_K(24)>;
28 reg = <0x0 DT_SIZE_K(470)>;
35 reg = <0x75800 DT_SIZE_K(30)>;
Dnrf54l10.dtsi10 reg = <0x20000000 DT_SIZE_K(144)>;
11 ranges = <0x0 0x20000000 DT_SIZE_K(144)>;
19 reg = <0x20024000 DT_SIZE_K(48)>;
22 ranges = <0x0 0x20024000 DT_SIZE_K(48)>;
28 reg = <0x0 DT_SIZE_K(960)>;
35 reg = <0xf0000 DT_SIZE_K(62)>;
Dnrf54l15.dtsi10 reg = <0x20000000 DT_SIZE_K(188)>;
11 ranges = <0x0 0x20000000 DT_SIZE_K(188)>;
19 reg = <0x2002f000 DT_SIZE_K(68)>;
22 ranges = <0x0 0x2002f000 DT_SIZE_K(68)>;
28 reg = <0x0 DT_SIZE_K(1428)>;
35 reg = <0x165000 DT_SIZE_K(96)>;

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