1/*
2 * Copyright (c) 2024 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/dts-v1/;
8
9#include <nordic/nrf54l10_cpuapp.dtsi>
10#include "nrf54l_05_10_15_cpuapp_common.dtsi"
11
12/ {
13	compatible = "nordic,nrf54l15dk_nrf54l10-cpuapp";
14	model = "Nordic nRF54L15 DK nRF54L10 Application MCU";
15
16	chosen {
17		zephyr,code-partition = &slot0_partition;
18		zephyr,sram = &cpuapp_sram;
19	};
20};
21
22/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
23&cpuapp_sram {
24	reg = <0x20000000 DT_SIZE_K(192)>;
25	ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
26};
27
28&cpuapp_rram {
29	reg = <0x0 DT_SIZE_K(1022)>;
30};
31
32/* These partition sizes assume no FLPR area in RRAM */
33&cpuapp_rram {
34	partitions {
35		compatible = "fixed-partitions";
36		#address-cells = <1>;
37		#size-cells = <1>;
38		boot_partition: partition@0 {
39			label = "mcuboot";
40			reg = <0x0 DT_SIZE_K(64)>;
41		};
42		slot0_partition: partition@10000 {
43			label = "image-0";
44			reg = <0x10000 DT_SIZE_K(230)>;
45		};
46		slot0_ns_partition: partition@49800 {
47			label = "image-0-nonsecure";
48			reg = <0x49800 DT_SIZE_K(230)>;
49		};
50		slot1_partition: partition@83000 {
51			label = "image-1";
52			reg = <0x83000 DT_SIZE_K(230)>;
53		};
54		slot1_ns_partition: partition@bc800 {
55			label = "image-1-nonsecure";
56			reg = <0xbc800 DT_SIZE_K(230)>;
57		};
58		storage_partition: partition@f6000 {
59			label = "storage";
60			reg = <0xf6000 DT_SIZE_K(38)>;
61		};
62	};
63};
64