Searched full:dll (Results 1 – 17 of 17) sorted by relevance
| /Zephyr-latest/dts/bindings/qspi/ |
| D | nxp,s32-qspi.yaml | 139 a-dll-mode:
147 DLL mode. The supported modes depends on the SoC.
150 a-dll-freq-enable:
156 a-dll-ref-counter:
161 Select the "n+1" interval of DLL phase detection and reference delay
166 a-dll-resolution:
171 Minimum resolution for DLL phase detector to remain locked/unlocked based
176 a-dll-coarse-delay:
182 is used to overwrite DLL-generated delay values.
186 a-dll-fine-delay:
[all …]
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| /Zephyr-latest/soc/nxp/imxrt/imxrt6xx/cm33/ |
| D | flash_clock_setup.c | 41 /* Need to wait DLL locked if DLL enabled */ in flash_init()
71 * to ensure the DLL is locked. in flash_init()
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| /Zephyr-latest/soc/nxp/imxrt/imxrt5xx/cm33/ |
| D | flash_clock_setup.c | 45 /* Need to wait DLL locked if DLL enabled */ in flash_init()
66 * the DLL is locked. in flash_init()
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| /Zephyr-latest/scripts/pylib/pytest-twister-harness/ |
| D | .gitignore | 1 # Byte-compiled / optimized / DLL files
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| /Zephyr-latest/samples/subsys/usb/inf/ |
| D | zephyr_cdc_acm.inf | 55 HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
83 HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider"
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| /Zephyr-latest/drivers/sdhc/ |
| D | sdhc_cdns_ll.c | 210 * This register holds the control for the Master DLL logic. in sdhc_cdns_program_phy_reg()
224 * This register holds the control for the slave DLL logic. in sdhc_cdns_program_phy_reg()
375 /* Enable DLL reset */ in sdhc_cdns_host_set_clk()
381 /* Release DLL reset */ in sdhc_cdns_host_set_clk()
512 /* Enable DLL reset */ in sdhc_cdns_set_clk()
518 /* Release DLL reset */ in sdhc_cdns_set_clk()
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| D | imx_usdhc.c | 278 /* Disable DLL */ in imx_usdhc_reset()
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| /Zephyr-latest/scripts/west_commands/runners/ |
| D | jlink.py | 189 # pylink 0.14.0/0.14.1 exposes JLink SDK DLL (libjlinkarm) in
198 libname = Library.get_appropriate_windows_sdk_name() + '.dll'
209 version = int(lib.dll().JLINKARM_GetDLLVersion())
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| /Zephyr-latest/drivers/serial/ |
| D | uart_lpc11u6x.h | 100 volatile uint32_t dll; /* Divisor latch LSB */ member
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| D | uart_lpc11u6x.c | 64 /* Enable access to dll & dlm registers */ in lpc11u6x_uart0_write_divisor()
66 uart0->dll = div & 0xFF; in lpc11u6x_uart0_write_divisor()
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| D | uart_smartbond.c | 54 /* DLH=cfg[23:16] DLL=cfg[15:8] DLF=cfg[7:0] */
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| /Zephyr-latest/arch/x86/zefi/ |
| D | zefi.py | 138 # Convert it to a PE-COFF DLL.
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| /Zephyr-latest/drivers/can/ |
| D | can_renesas_ra.c | 91 (1U << R_CANFD_CFDGCFG_DCS_Pos)) /* DLL Clock Select: CANFDCLK */
914 * (RAM clock rate / 2) >= DLL rate in can_renesas_module_clock_init()
915 * (CANFD operation clock rate) >= DLL rate in can_renesas_module_clock_init()
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| /Zephyr-latest/drivers/memc/ |
| D | memc_mcux_flexspi.c | 115 * We need to update the DLL value before we call clock_control_get_rate, in memc_flexspi_update_clock()
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| /Zephyr-latest/drivers/flash/ |
| D | flash_cadence_nand_ll.h | 108 /* Mini controller DLL PHY controller register field offsets */
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| D | flash_cadence_nand_ll.c | 276 /* Reset DLL PHY */ in cdns_nand_set_opr_mode()
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| /Zephyr-latest/boards/nxp/mr_canhubk3/ |
| D | mr_canhubk3.dts | 332 a-dll-mode = "BYPASSED";
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