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/Zephyr-latest/dts/bindings/interrupt-controller/
Dcypress,psoc6-intmux.yaml3 # SPDX-License-Identifier: Apache-2.0
8 The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
10 to be processed in the Cortex-M0+ CPU.
13 configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
17 Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
21 configuration and how the Cortex-M0+ NVIC sources are organized. Each
22 channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
24 Cortex-M0+ NVIC controller line.
31 In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
33 the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
[all …]
/Zephyr-latest/soc/infineon/cat1a/
DKconfig3 # SPDX-License-Identifier: Apache-2.0
32 bool "Dual-core support [activate Cortex-M4]"
35 Cortex-M0 CPU should boot Cortex-M4
38 ## PSOC™ 6 Cortex M0+ prebuilt images
40 prompt "PSOC™ 6 Cortex M0+ prebuilt images"
42 Choose the prebuilt application image to be executed on the Cortex-M0+ core of the PSOC™ 6
43 dual-core MCU. The image is responsible for booting the Cortex-M4 on the device.
48 DeepSleep prebuilt application image is executed on the Cortex-M0+ core of the PSOC™ 6 BLE
49 dual-core MCU.The image is provided as C array ready to be compiled as part of the Cortex-M4
50 application. The Cortex-M0+ application code is placed to internal flash by the Cortex-M4
/Zephyr-latest/samples/bluetooth/hci_uart/dts/arm/nordic/
Doverride.dtsi2 * ARM Cortex-M4 lowest priority value of 5, i.e. considering Zephyr reserved 2
4 * ARM Cortex-M0 lowest priority value of 3, i.e. we use it as Zephyr has no
5 * support for ZLI on Cortex-M0.
/Zephyr-latest/dts/bindings/cpu/
Darm,cortex-m0.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M0 CPU
6 compatible: "arm,cortex-m0"
Darm,cortex-m0+.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ARM Cortex-M0+ CPU
6 compatible: "arm,cortex-m0+"
/Zephyr-latest/include/zephyr/arch/arm/
Dasm_inline_gcc.h6 * SPDX-License-Identifier: Apache-2.0
34 /* On ARMv7-M and ARMv8-M Mainline CPUs, this function prevents regular
39 * On ARMv6-M and ARMv8-M Baseline CPUs, this function reads the value of
53 #error "Cortex-M0 and Cortex-M0+ require SoC specific support for cross core synchronisation." in arch_irq_lock()
76 /* On Cortex-M0/M0+, this enables all interrupts if they were not
/Zephyr-latest/soc/infineon/cat1a/psoc6_legacy/
Dcypress_psoc6_dt.h3 * Copyright (c) 2020-2021 ATL Electronics
5 * SPDX-License-Identifier: Apache-2.0
23 * because Cortex-M0+ can handle a limited number of interrupts and have
44 * n - driver instance number
45 * isr - isr function to be called
47 * Cortex-M4 simple pass the parameter and constructs an usual NVIC
50 * The Cortex-M0+ must get from interrupt parent the interrupt line and
52 * Cortex-M0+ NVIC. The multiplexer is configured by CY_PSOC6_DT_NVIC_MUX_MAP
55 * see cypress,psoc6-int-mux.yaml for devicetree documentation.
58 /* Cortex-M0+
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/Zephyr-latest/arch/arm/core/cortex_m/
DKconfig1 # ARM Cortex-M platform configuration options
3 # Copyright (c) 2014-2015 Wind River Systems, Inc.
4 # SPDX-License-Identifier: Apache-2.0
10 # if one select a different ARM Cortex Family (Cortex-A or Cortex-R)
17 This option signifies the use of a Cortex-M0 CPU
24 This option signifies the use of a Cortex-M0+ CPU
31 This option signifies the use of a Cortex-M1 CPU
38 This option signifies the use of a Cortex-M3 CPU
46 This option signifies the use of a Cortex-M4 CPU
54 This option signifies the use of a Cortex-M23 CPU
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/Zephyr-latest/boards/qemu/cortex_m0/doc/
Dindex.rst9 This configuration provides support for an ARM Cortex-M0 CPU and these devices:
25 +--------------+------------+----------------------+
28 | NVIC | on-chip | nested vectored |
30 +--------------+------------+----------------------+
31 | nRF | on-chip | serial port |
33 +--------------+------------+----------------------+
34 | nRF TIMER | on-chip | system clock |
35 +--------------+------------+----------------------+
42 ------------
47 -----------
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/Zephyr-latest/boards/qemu/cortex_m0/
Dboard.yml3 full_name: QEMU Emulation for ARM Cortex-M0
6 - name: nrf51822
DKconfig.qemu_cortex_m01 # QEMU Cortex-M0 board configuration
4 # SPDX-License-Identifier: Apache-2.0
DKconfig.defconfig1 # QEMU Cortex-M0 board configuration
4 # SPDX-License-Identifier: Apache-2.0
Dqemu_cortex_m0.yaml2 name: QEMU Emulation for Cortex-M0
5 - name: qemu
8 - zephyr
9 - gnuarmemb
10 - xtools
16 - net
17 - bluetooth
Dboard.cmake4 # SPDX-License-Identifier: Apache-2.0
8 set(QEMU_CPU_TYPE_${ARCH} cortex-m0)
10 -cpu ${QEMU_CPU_TYPE_${ARCH}}
11 -machine microbit
12 -nographic
13 -vga none
/Zephyr-latest/boards/cypress/cy8ckit_062_ble/doc/
Dindex.rst9 The PSOC 6 BLE Pioneer Kit (CY8CKIT-062-BLE) is a hardware platform that
12 The PSOC 6 BLE Pioneer Kit features the PSOC 63 MCU: a dual-core MCU, with a
13 150-MHz Arm Cortex-M4 as the primary application processor and a 100-MHz Arm
14 Cortex-M0+ that supports low-power operations, 1MB of Flash, 288KB of SRAM,
16 programmable digital blocks, and capacitive-sensing with CapSense.
19 512-Mb NOR flash, onboard programmer/debugger (KitProg2), USB Type-C power
20 delivery system (EZ-PD™ CCG3), 5-segment CapSense slider, two CapSense
24 The CY8CKIT-062-BLE package includes a CY8CKIT-028-EPD E-INK Display Shield
25 that contains a 2.7-inch E-INK display, a motion sensor, a thermistor, and a
27 Dongle that is factory-programmed to emulate a BLE GAP Central device,
[all …]
/Zephyr-latest/tests/subsys/llext/src/
Dmovwmovt_ext.c4 * SPDX-License-Identifier: Apache-2.0
9 * (except Cortex-M0, M0+ and M1, that don't support them)
/Zephyr-latest/soc/infineon/cat1a/common/
Dram_cm0image.ld5 * SPDX-License-Identifier: Apache-2.0
8 /* Cortex-M0+ application ram image area */
Drom_cm0image.ld5 * SPDX-License-Identifier: Apache-2.0
8 /* Cortex-M0+ application flash image area */
/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc54xxx_m0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
12 /delete-node/ cpu@0;
15 compatible = "arm,cortex-m0+";
21 arm,num-irq-priority-bits = <2>;
/Zephyr-latest/soc/atmel/sam0/samr34/
DKconfig.soc5 # SPDX-License-Identifier: Apache-2.0
11 Enable support for Atmel SAMR34 Cortex-M0+ microcontrollers.
/Zephyr-latest/soc/atmel/sam0/samr35/
DKconfig.soc5 # SPDX-License-Identifier: Apache-2.0
11 Enable support for Atmel SAMR35 Cortex-M0+ microcontrollers.
/Zephyr-latest/samples/subsys/debug/debugmon/
DREADME.rst1 .. zephyr:code-sample:: debugmon
4 Configure the Debug Monitor feature on a Cortex-M processor.
17 .. _debugmon-sample-requirements:
24 #. Support Debug Monitor feature (available on Cortex-M processors with the exception of Cortex-M0)
34 .. zephyr-app-commands::
35 :zephyr-app: samples/subsys/debug/debugmon
/Zephyr-latest/soc/atmel/sam0/samr21/
DKconfig.soc5 # SPDX-License-Identifier: Apache-2.0
11 Enable support for Atmel SAMR21 Cortex-M0+ microcontrollers.
/Zephyr-latest/cmake/
Dgcc-m-cpu.cmake1 # SPDX-License-Identifier: Apache-2.0
3 # Determines what argument to give to -mcpu= based on the
8 set(GCC_M_CPU cortex-m0)
10 set(GCC_M_CPU cortex-m0plus)
12 set(GCC_M_CPU cortex-m1)
14 set(GCC_M_CPU cortex-m3)
16 set(GCC_M_CPU cortex-m4)
18 set(GCC_M_CPU cortex-m7)
20 set(GCC_M_CPU cortex-m23)
23 set(GCC_M_CPU cortex-m33)
[all …]
/Zephyr-latest/soc/nxp/lpc/lpc54xxx/
Dsoc.c4 * SPDX-License-Identifier: Apache-2.0
11 * This module provides routines to initialize and support board-level
37 memcpy((uint32_t *)((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA), \
74 /* Set up clock selectors - Attach clocks to the peripheries */ in clock_init()
122 * but M0 core does not. install one here to call SystemInit.
152 SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM2_MASK; in _slave_init()
160 * and then detects its identity (Cortex-M0, slave) and checks in _slave_init()
163 * Make sure the startup code for the current core (Cortex-M4) is in _slave_init()
164 * appropriate and shareable with the Cortex-M0 core! in _slave_init()
166 SYSCON->CPBOOT = SYSCON_CPBOOT_BOOTADDR( in _slave_init()
[all …]

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