Lines Matching +full:cortex +full:- +full:m0

3 # SPDX-License-Identifier: Apache-2.0
8   The PSOC 6 Cortex-M0+ NVIC can handle up to 32 interrupts. This means that
10   to be processed in the Cortex-M0+ CPU.
13   configure the 32 NVIC lines for Cortex-M0+ CPU. Each register handles up to
17   Cortex-M0+ NVIC controller. Note that Cortex-M4 have all interrupt sources
21   configuration and how the Cortex-M0+ NVIC sources are organized. Each
22   channel chX represents a Cortex-M0+ NVIC line and it stores a vector number.
24   Cortex-M0+ NVIC controller line.
31   In practical terms, the Cortex-M0+ requires user to define all NVIC interrupt
33   the Cortex-M0+ Interrupt Multiplexer and interrupts can be processed.
39   Cortex-M0+ NVIC:
47   In order to enable gpio_prt0 interrupt at Cortex-M0+ an interrupt parent
52     interrupt-parent = <&intmux_ch20>;
59   These results in Cortex-M0+ NVIC line 20 handling PSOC 6 interrupt source 2.
64   2) The interrupt sources are shared between Cortex-M0+/M4. This means, they
66   3) User can change priority at Cortex-M0+ NVIC by changing interrupt channels
67      at interrupt-parent properties.
68   4) Only the peripherals used by Cortex-M0+ should be configured.
70 compatible: "cypress,psoc6-intmux"