Searched full:clocked (Results 1 – 25 of 64) sorted by relevance
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| /Zephyr-latest/dts/bindings/timer/ |
| D | st,stm32-lptim.yaml | 29 Prescaler allows to achieve higher LPTIM timeout (up to 256s when lptim clocked by LSE)
35 For example, when LPTIM is clocked by the LSE (32768Hz) and st,prescaler = <32>:
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| /Zephyr-latest/boards/digilent/zybo/ |
| D | zybo_defconfig | 3 # The GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x)
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu700/ |
| D | soc.h | 14 /* On FU740, peripherals are clocked by PCLK. */
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| /Zephyr-latest/dts/bindings/spi/ |
| D | nordic,nrf-spis.yaml | 15 Default character. Character clocked out when the slave was not
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| D | nxp,lpc-spi.yaml | 39 Default character clocked out when the TX buffer pointer is NULL.
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| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | soc.h | 15 * On FE310 and FU540, peripherals such as SPI, UART, I2C and PWM are clocked
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu500/ |
| D | soc.h | 15 * On FE310 and FU540, peripherals such as SPI, UART, I2C and PWM are clocked
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| /Zephyr-latest/arch/arc/core/ |
| D | timestamp.c | 21 * This function returns a 64-bit bit time stamp value that is clocked
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| /Zephyr-latest/dts/bindings/pwm/ |
| D | nxp,ftm-pwm.yaml | 30 passes through a sychronizer clocked by the FTM bus interface clock.
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| /Zephyr-latest/dts/bindings/clock/ |
| D | st,stm32wb0-rcc.yaml | 30 On STM32WB0, all slow clock devices are clocked from the same
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| /Zephyr-latest/dts/bindings/mipi-dbi/ |
| D | zephyr,mipi-dbi-bitbang.yaml | 42 Clocked enable/strobe pin for type A (Motorola 6800) mode, unused for type B (Intel 8080).
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| /Zephyr-latest/subsys/task_wdt/ |
| D | Kconfig | 59 is clocked by an inaccurate low-speed RC oscillator.
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| /Zephyr-latest/drivers/timer/ |
| D | Kconfig.stm32_lptim | 70 but LPTIM is not clocked in standby mode. These chips usually have
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| D | Kconfig.cortex_m_systick | 54 but SysTick is not clocked in low power mode. These chips usually have
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| D | smartbond_timer.c | 111 * When LP clock is RCX, the watchdog is clocked by RCX clock in sys_clock_set_timeout()
117 * When LP clock is not RCX, the watchdog is clocked by RC32K in sys_clock_set_timeout()
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| D | stm32_lptim_timer.c | 54 * - system clock based on an LPTIM instance, clocked by LSI or LSE
75 * This is for example about of 65000 x 2000ms when clocked by LSI
96 * case because the LPTIM is not clocked in some low power mode state.
260 * is treated as a lptim off ; never waking up ; lptim not clocked anymore in sys_clock_set_timeout()
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| /Zephyr-latest/boards/nuvoton/numaker_m2l31ki/ |
| D | numaker_m2l31ki.dts | 78 /* On enabled, usbd is required to be clocked in 48MHz. */
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| /Zephyr-latest/drivers/usb/udc/ |
| D | udc_dwc2.h | 31 /* Called while waiting for bits that require PHY to be clocked */
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| /Zephyr-latest/boards/nuvoton/numaker_pfm_m467/ |
| D | numaker_pfm_m467.dts | 123 /* On enabled, usbd is required to be clocked in 48MHz. */
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| /Zephyr-latest/drivers/spi/ |
| D | Kconfig.nrfx | 76 clocked out when RXD.MAXCNT == 1 and TXD.MAXCNT <= 1).
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| /Zephyr-latest/soc/st/stm32/common/ |
| D | soc_config.c | 44 * - one of the DMA is clocked. in st_stm32_common_config()
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| /Zephyr-latest/samples/boards/espressif/deep_sleep/ |
| D | README.rst | 10 CPU, majority of RAM, and digital peripherals that are clocked from APB_CLK to
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| /Zephyr-latest/subsys/mgmt/ec_host_cmd/backends/ |
| D | ec_host_cmd_backend_shi.h | 54 * Padding bytes which are clocked out after the end of a response packet.
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| /Zephyr-latest/samples/boards/st/power_mgmt/serial_wakeup/ |
| D | README.rst | 25 - Clocked by an oscillator available in Stop mode (LSE, LSI) or an oscillator capable
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_stm32_ll_wb0.c | 418 * If Direct HSE is enabled, the high-speed tree is clocked by HSE @ 32MHz. in stm32_clock_control_get_subsys_rate()
419 * Otherwise, the high-speed tree is clocked by the RC64MPLL clock @ 64MHz. in stm32_clock_control_get_subsys_rate()
464 /* All peripherals on AHB0 are clocked by CLK_SYS. */ in stm32_clock_control_get_subsys_rate()
493 * it is clocked by two sources that run at different frequencies, in stm32_clock_control_get_subsys_rate()
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