| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/ |
| D | test_stm32_clock_configuration_i2c.c | 28 static void i2c_set_clock(const struct stm32_pclken *clk) in i2c_set_clock() argument
35 (clock_control_subsys_t) clk, in i2c_set_clock()
43 if (clk->bus == STM32_SRC_HSI) { in i2c_set_clock()
47 } else if (clk->bus == STM32_SRC_SYSCLK) { in i2c_set_clock()
52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in i2c_set_clock()
55 /* Test status of the used clk source */ in i2c_set_clock()
57 (clock_control_subsys_t)clk); in i2c_set_clock()
58 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "I2C1 clk src must to be on"); in i2c_set_clock()
60 /* Test get_rate(srce clk) */ in i2c_set_clock()
62 (clock_control_subsys_t) clk, in i2c_set_clock()
[all …]
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| D | test_stm32_clock_configuration_i2s.c | 52 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in ZTEST()
55 /* Test get_rate(srce clk) */ in ZTEST()
59 zassert_true((r == 0), "Could not get I2S clk srce freq"); in ZTEST()
63 "Expected freq: %d Hz. Actual clk: %d Hz", in ZTEST()
68 /* Test clock_off(gating clk) */ in ZTEST()
71 zassert_true((r == 0), "Could not disable I2S gating clk"); in ZTEST()
73 zassert_true(!__HAL_RCC_SPI2_IS_CLK_ENABLED(), "I2S2 gating clk should be off"); in ZTEST()
74 TC_PRINT("I2S2 gating clk off\n"); in ZTEST()
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| D | test_stm32_clock_configuration_sdmmc.c | 48 /* CLK 48 is enabled through the clock-mux */ in ZTEST()
68 "Expected SDMMC src: CLK 48 (0x%lx). Actual src: 0x%x", in ZTEST()
75 zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src); in ZTEST()
78 /* Test get_rate(srce clk) */ in ZTEST()
110 zassert_true((r == 0), "Could not get SDMMC clk srce freq"); in ZTEST()
117 "Expected freq: %d Hz. Actual clk: %d Hz", in ZTEST()
122 /* Test clock_off(gating clk) */ in ZTEST()
125 zassert_true((r == 0), "Could not disable SDMMC gating clk"); in ZTEST()
127 zassert_true(!__HAL_RCC_SDIO_IS_CLK_ENABLED(), "SDMMC gating clk should be off"); in ZTEST()
128 TC_PRINT("SDMMC gating clk off\n"); in ZTEST()
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| D | test_stm32_clock_configuration_lptim.c | 60 zassert_true(0, "Unexpected domain clk (%d)", dev_actual_clk_src); in ZTEST()
63 /* Test get_rate(srce clk) */ in ZTEST()
67 zassert_true((r == 0), "Could not get LPTIM1 clk srce freq"); in ZTEST()
83 zassert_true((r == 0), "Could not get LPTIM1 clk freq"); in ZTEST()
96 zassert_true((r == 0), "Could not disable LPTIM1 gating clk"); in ZTEST()
98 zassert_true(!__HAL_RCC_LPTIM1_IS_CLK_ENABLED(), "LPTIM1 gating clk should be off"); in ZTEST()
99 TC_PRINT("LPTIM1 gating clk off\n"); in ZTEST()
101 /* Test clock_off(domain clk) */ in ZTEST()
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| D | test_stm32_clock_configuration_adc.c | 112 zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src); in ZTEST()
115 /* Test status of the used clk source */ in ZTEST()
118 zassert_true((status == CLOCK_CONTROL_STATUS_ON), "ADC1 clk src must to be on"); in ZTEST()
120 /* Test get_rate(srce clk) */ in ZTEST()
124 zassert_true((r == 0), "Could not get ADC1 clk srce freq"); in ZTEST()
143 zassert_true((r == 0), "Could not disable ADC1 gating clk"); in ZTEST()
145 zassert_true(!ADC_IS_CLK_ENABLED(), "ADC1 gating clk should be off"); in ZTEST()
146 TC_PRINT("ADC1 gating clk off\n"); in ZTEST()
148 /* Test clock_off(domain clk) */ in ZTEST()
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| /Zephyr-latest/drivers/usb/device/ |
| D | usb_dc_dw_stm32.h | 22 static inline int clk_enable_st_stm32f4_fsotg(const struct usb_dw_stm32_clk *const clk) in clk_enable_st_stm32f4_fsotg() argument
26 if (!device_is_ready(clk->dev)) { in clk_enable_st_stm32f4_fsotg()
30 if (clk->pclken_len > 1) { in clk_enable_st_stm32f4_fsotg()
33 ret = clock_control_configure(clk->dev, in clk_enable_st_stm32f4_fsotg()
34 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
40 ret = clock_control_get_rate(clk->dev, in clk_enable_st_stm32f4_fsotg()
41 (void *)&clk->pclken[1], in clk_enable_st_stm32f4_fsotg()
52 return clock_control_on(clk->dev, (void *)&clk->pclken[0]); in clk_enable_st_stm32f4_fsotg()
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_arm_scmi.c | 7 #include <zephyr/drivers/firmware/scmi/clk.h>
20 clock_control_subsys_t clk, bool on) in scmi_clock_on_off() argument
29 clk_id = POINTER_TO_UINT(clk); in scmi_clock_on_off()
43 static int scmi_clock_on(const struct device *dev, clock_control_subsys_t clk) in scmi_clock_on() argument
45 return scmi_clock_on_off(dev, clk, true); in scmi_clock_on()
48 static int scmi_clock_off(const struct device *dev, clock_control_subsys_t clk) in scmi_clock_off() argument
50 return scmi_clock_on_off(dev, clk, false); in scmi_clock_off()
54 clock_control_subsys_t clk, uint32_t *rate) in scmi_clock_get_rate() argument
62 clk_id = POINTER_TO_UINT(clk); in scmi_clock_get_rate()
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| D | clock_control_rpi_pico.c | 57 #define CLK_SRC_IS(clk, src) \ argument
58 DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), 0), \
72 #define CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, clk) argument
73 #define SRC_CLOCK(clk) DT_STRING_TOKEN_BY_IDX(DT_INST_CLOCKS_CTLR_BY_NAME(0, clk), \ argument
75 #define SRC_CLOCK_FREQ(clk) _CONCAT(CLOCK_FREQ_, SRC_CLOCK(clk)) argument
100 #define CLOCK_AUX_SOURCE(clk) _CONCAT(_CONCAT(AUXSTEM_, clk), _CONCAT(AUXSRC_, SRC_CLOCK(clk))) argument
175 enum rpi_pico_clkid clk; member
331 clock_hw_t *clock_hw = &config->clocks_regs->clk[id]; in rpi_pico_get_clock_src()
344 clock_hw_t *clock_hw = &clocks_hw->clk[id]; in rpi_pico_get_clock_src()
367 clock_hw_t *clock_hw = &clocks_hw->clk[id]; in rpi_pico_get_clock_src()
[all …]
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| D | clock_control_smartbond.c | 47 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk);
208 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_on() local
213 switch (clk) { in smartbond_clock_control_on()
232 pll_requests = 1 << (clk - SMARTBOND_CLK_PLL96M); in smartbond_clock_control_on()
260 enum smartbond_clock clk = (enum smartbond_clock)(sub_system); in smartbond_clock_control_off() local
265 switch (clk) { in smartbond_clock_control_off()
303 pll_requests &= ~(1 << (clk - SMARTBOND_CLK_PLL96M)); in smartbond_clock_control_off()
327 static enum smartbond_clock smartbond_source_clock(enum smartbond_clock clk) in smartbond_source_clock() argument
342 if (clk == SMARTBOND_CLK_SYS_CLK) { in smartbond_source_clock()
343 clk = sys_clk_src[CRG_TOP->CLK_CTRL_REG & in smartbond_source_clock()
[all …]
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| D | clock_control_r8a7795_cpg_mssr.c | 115 static int r8a7795_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a7795_cpg_core_clock_endisable() argument
122 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in r8a7795_cpg_core_clock_endisable()
128 if (clk->rate > 0) { in r8a7795_cpg_core_clock_endisable()
130 uintptr_t rate = clk->rate; in r8a7795_cpg_core_clock_endisable()
132 ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk, in r8a7795_cpg_core_clock_endisable()
150 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in r8a7795_cpg_mssr_start_stop() local
157 if (clk->domain == CPG_MOD) { in r8a7795_cpg_mssr_start_stop()
162 ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); in r8a7795_cpg_mssr_start_stop()
164 } else if (clk->domain == CPG_CORE) { in r8a7795_cpg_mssr_start_stop()
165 ret = r8a7795_cpg_core_clock_endisable(dev, clk, enable); in r8a7795_cpg_mssr_start_stop()
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| D | clock_control_r8a779f0_cpg_mssr.c | 110 static int r8a779f0_cpg_core_clock_endisable(const struct device *dev, struct rcar_cpg_clk *clk, in r8a779f0_cpg_core_clock_endisable() argument
117 clk_info = rcar_cpg_find_clk_info_by_module_id(dev, clk->domain, clk->module); in r8a779f0_cpg_core_clock_endisable()
123 if (clk->rate > 0) { in r8a779f0_cpg_core_clock_endisable()
125 uintptr_t rate = clk->rate; in r8a779f0_cpg_core_clock_endisable()
127 ret = rcar_cpg_set_rate(dev, (clock_control_subsys_t)clk, in r8a779f0_cpg_core_clock_endisable()
144 struct rcar_cpg_clk *clk = (struct rcar_cpg_clk *)sys; in r8a779f0_cpg_mssr_start_stop() local
151 if (clk->domain == CPG_MOD) { in r8a779f0_cpg_mssr_start_stop()
156 ret = rcar_cpg_mstp_clock_endisable(DEVICE_MMIO_GET(dev), clk->module, enable); in r8a779f0_cpg_mssr_start_stop()
158 } else if (clk->domain == CPG_CORE) { in r8a779f0_cpg_mssr_start_stop()
159 ret = r8a779f0_cpg_core_clock_endisable(dev, clk, enable); in r8a779f0_cpg_mssr_start_stop()
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| /Zephyr-latest/dts/bindings/i2c/ |
| D | atmel,sam-i2c-twim.yaml | 20 std-clk-slew-lim = <0>;
21 std-clk-strength-low = "0.5";
25 hs-clk-slew-lim = <0>;
26 hs-clk-strength-high = "0.5";
27 hs-clk-strength-low = "0.5";
54 std-clk-slew-lim:
59 std-clk-strength-low to fine tune the TWCK slope.
66 std-clk-strength-low:
114 hs-clk-slew-lim:
119 should be adjusted with both hs-clk-strength-high and
[all …]
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| /Zephyr-latest/tests/net/ptp/clock/src/ |
| D | main.c | 308 const struct device *clk; in iface_cb() local
315 clk = net_eth_get_ptp_clock(iface); in iface_cb()
316 if (!clk) { in iface_cb()
415 const struct device *clk; in test_ptp_clock_interfaces() local
419 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
420 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
424 clk = net_eth_get_ptp_clock(eth_interfaces[idx]); in test_ptp_clock_interfaces()
425 zassert_not_null(clk, "Clock not found for interface %p\n", in test_ptp_clock_interfaces()
428 clk = net_eth_get_ptp_clock(eth_interfaces[non_ptp_interface]); in test_ptp_clock_interfaces()
429 zassert_is_null(clk, "Clock found for interface %p\n", in test_ptp_clock_interfaces()
[all …]
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| /Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/src/ |
| D | test_stm32_clock_configuration.c | 57 zassert_true((r == 0), "Could not configure SPI domain clk"); in ZTEST()
58 TC_PRINT("SPI1 domain clk configured\n"); in ZTEST()
60 /* Test clk source */ in ZTEST()
72 zassert_true(1, "Unexpected clk src (0x%x)", spi1_actual_domain_clk); in ZTEST()
75 /* Test get_rate(source clk) */ in ZTEST()
79 zassert_true((r == 0), "Could not get SPI clk freq"); in ZTEST()
83 "Expected SPI clk: %d. Actual: %d", in ZTEST()
96 "Expected SPI clk freq: %d. Actual: %d", in ZTEST()
108 /* Test clock_off(domain clk) */ in ZTEST()
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| /Zephyr-latest/drivers/fpga/ |
| D | fpga_ice40_bitbang.c | 47 struct gpio_dt_spec clk; member
71 volatile gpio_port_pins_t *clear, gpio_port_pins_t clk, size_t n) in fpga_ice40_send_clocks() argument
74 *clear |= clk; in fpga_ice40_send_clocks()
76 *set |= clk; in fpga_ice40_send_clocks()
83 gpio_port_pins_t clk, gpio_port_pins_t pico, uint8_t *z, in fpga_ice40_spi_send_data() argument
96 *clear |= clk; in fpga_ice40_spi_send_data()
107 *set |= clk; in fpga_ice40_spi_send_data()
127 gpio_port_pins_t clk; in fpga_ice40_load() local
135 if (!device_is_ready(config_bitbang->clk.port)) { in fpga_ice40_load()
136 LOG_ERR("%s: GPIO for clk is not ready", dev->name); in fpga_ice40_load()
[all …]
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| /Zephyr-latest/boards/atmel/sam/sam4l_ek/ |
| D | sam4l_ek.dts | 71 clk = <4>;
81 std-clk-slew-lim = <0>;
82 std-clk-strength-low = "0.5";
86 hs-clk-slew-lim = <0>;
87 hs-clk-strength-high = "0.5";
88 hs-clk-strength-low = "0.5";
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,numaker-pcc.yaml | 15 - clock-module-index # Same as u32ModuleIdx on invoking BSP CLK driver CLK_SetModuleClock()
16 - clock-source # Same as u32ClkSrc on invoking BSP CLK driver CLK_SetModuleClock()
17 - clock-divider # Same as u32ClkDiv on invoking BSP CLK driver CLK_SetModuleClock()
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| D | intel,adsp-shim-clkctl.yaml | 9 adsp-clkctl-clk-wovcro:
14 adsp-clkctl-clk-lpro:
18 adsp-clkctl-clk-hpro:
22 adsp-clkctl-clk-ipll:
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| /Zephyr-latest/samples/sensor/lps22hh_i3c/boards/ |
| D | mimxrt685_evk_mimxrt685s_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
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| /Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/boards/ |
| D | mimxrt685_evk_mimxrt685s_cm33.overlay | 14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
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| /Zephyr-latest/dts/arm/st/f2/ |
| D | stm32f207.dtsi | 17 clock-names = "stmmaceth", "mac-clk-tx",
18 "mac-clk-rx", "mac-clk-ptp";
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| /Zephyr-latest/dts/arm/st/f4/ |
| D | stm32f407.dtsi | 17 clock-names = "stmmaceth", "mac-clk-tx",
18 "mac-clk-rx", "mac-clk-ptp";
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| /Zephyr-latest/dts/bindings/ethernet/ |
| D | infineon,xmc4xxx-ethernet.yaml | 59 rmii-rx-clk-port-ctrl:
62 If the RMII interface is used it connects GPIO to the rmii-clk signal.
63 Otherwise, if the MII interface is used, then it connects to the Receive clock (rx-clk)
113 tx-clk-port-ctrl:
114 description: Transmit clock (tx-clk) GPIO connection. Only used for MII interface.
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| /Zephyr-latest/drivers/memc/ |
| D | memc_stm32.c | 44 const struct device *clk; in memc_stm32_init() local
54 clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in memc_stm32_init()
56 if (!device_is_ready(clk)) { in memc_stm32_init()
61 r = clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]); in memc_stm32_init()
69 r = clock_control_configure(clk, (clock_control_subsys_t)&config->pclken[1], NULL); in memc_stm32_init()
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| /Zephyr-latest/dts/bindings/i3c/ |
| D | nxp,mcux-i3c.yaml | 25 clk-divider:
30 clk-divider-tc:
35 clk-divider-slow:
|
