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/Zephyr-latest/dts/arm/st/h7/
Dstm32h747.dtsi20 clocks = <&rcc STM32_CLOCK(APB3, 4U)>,
23 resets = <&rctl STM32_RESET(APB3, 4U)>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_devices/boards/
Dcore_init.overlay58 /delete-property/ apb3-prescaler;
97 apb3-prescaler = <1>;
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcm-pcc.yaml18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
146 apb3-prescaler:
150 APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
Dnuvoton,npcx-pcc.yaml18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
145 apb3-prescaler:
149 APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
Dst,stm32u5-rcc.yaml17 apb3-prescaler:
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32u5_core/boards/
Dhsi_16.overlay22 apb3-prescaler = <1>;
Dmsis_24.overlay28 apb3-prescaler = <1>;
Dmsis_48.overlay28 apb3-prescaler = <1>;
Dhse_16.overlay29 apb3-prescaler = <1>;
Dpll_hsi_160.overlay31 apb3-prescaler = <1>;
Dpll_hsi_40.overlay31 apb3-prescaler = <1>;
Dpll_hsi_fracn_160.overlay33 apb3-prescaler = <1>;
Dpll_msis_160.overlay37 apb3-prescaler = <1>;
Dpll_msis_ahb_2_40.overlay37 apb3-prescaler = <1>;
Dpll_hse_160.overlay38 apb3-prescaler = <1>;
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32h5_core/boards/
Dcsi4.overlay23 apb3-prescaler = <1>;
Dhse24.overlay29 apb3-prescaler = <1>;
Dhse25.overlay30 apb3-prescaler = <1>;
Dpll_csi_ahb_2_100.overlay33 apb3-prescaler = <1>;
Dpll_csi_100.overlay34 apb3-prescaler = <1>;
Dpll_csi_240.overlay34 apb3-prescaler = <1>;
Dpll_hse24_100.overlay39 apb3-prescaler = <1>;
Dpll_hse24_240.overlay39 apb3-prescaler = <1>;
Dpll_hse24_ahb_2_100.overlay34 apb3-prescaler = <1>;
Dpll_hsi_240.overlay34 apb3-prescaler = <1>;

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