Home
last modified time | relevance | path

Searched full:a0 (Results 1 – 25 of 382) sorted by relevance

12345678910>>...16

/Zephyr-latest/arch/xtensa/core/
Duserspace.S29 movi a0, xtensa_is_user_context_epc
31 bne a0, a2, _not_checking_user_context
36 movi a0, PS_RING_MASK
38 and a2, a2, a0
49 rsr a0, ZSR_A0SAVE
56 rsr a0, ZSR_CPU
57 l32i a0, a0, ___cpu_t_current_OFFSET
58 l32i a0, a0, _thread_offset_to_psp
60 addi a0, a0, -___xtensa_irq_bsa_t_SIZEOF
62 s32i a1, a0, ___xtensa_irq_bsa_t_scratch_OFFSET
[all …]
Dxtensa_asm2_util.S18 * (so you have to save off A0, but no other registers need to be
154 l32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
155 wsr a0, ZSR_EPC
156 l32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
157 wsr a0, ZSR_EPS
168 l32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
169 wsr a0, SAR
171 l32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
172 wsr a0, LBEG
173 l32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
[all …]
Dwindow_vectors.S30 * all the registers from call[i+1]'s window. In particular, a0 and a1 must be
47 * a0-a3 are registers to be saved;
56 s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
69 * a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
78 l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
86 * "free". All interruptee's regs are intact except a0 which is saved
100 rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */
101 rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */
105 rsr a4, ZSR_A0SAVE /* restore original a0 (now in a4) */
112 rotw -1 /* original a0 goes to a8 */
[all …]
Dcrt1.S67 * Keep a0 zero. It is used to initialize a few things.
74 movi a0, 0 /* keep this register zero. */
146 /* Clear a0 again as possible CALLX to __memmap_init changed it. */
147 movi a0, 0
155 * a0 = 0
171 s32i a0, a8, 0 /* clear 4 bytes to make len multiple of 8 */
174 s32i a0, a8, 0 /* clear 8 bytes to make len multiple of 16 */
175 s32i a0, a8, 4
179 s32i a0, a8, 0 /* clear 16 bytes at a time... */
180 s32i a0, a8, 4
[all …]
DREADME_WINDOWS.rst13 visible as A0-A15.
15 The first quad (A0-A3) is pointed to by a special register called
18 (respectively) A0-A3, A4-A7, A8-A11, and A12-A15.
24 A0).
31 the top two bits of the return address placed in A0.
39 top two bits from the return address in A0 and subtracts that value
61 being brought into A0-A3 (i.e. the new WINDOWBASE) has a set bit
86 The spill area for a single frame's A0-A3 registers is not in its own
101 to write a function using only A0-A3 and CALL4 calls and ignore higher
103 the top of the stack frame, immediately below the parent call's A0-A3
/Zephyr-latest/include/zephyr/arch/riscv/
Dsyscall.h44 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke6()
53 : "+r" (a0) in arch_syscall_invoke6()
57 return a0; in arch_syscall_invoke6()
65 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke5()
73 : "+r" (a0) in arch_syscall_invoke5()
76 return a0; in arch_syscall_invoke5()
83 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke4()
90 : "+r" (a0) in arch_syscall_invoke4()
93 return a0; in arch_syscall_invoke4()
100 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke3()
[all …]
/Zephyr-latest/soc/openisa/rv32m1/
Dsoc_irq.S20 * With a0 == irq_num, this is equivalent to:
25 * that's calling us requires that a0 still contain irq_num
35 sll t1, t1, a0
55 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
56 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
57 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
61 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
62 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
63 sw t2, __soc_esf_t_lpcount1_OFFSET(a0)
70 lw t0, __soc_esf_t_lpstart0_OFFSET(a0)
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
D__arithmetic.S31 /* signed 32 bit multiplication. opcode of mul a0,a0,a1 is 0x02b50533 */
34 /* signed 32 bit division. opcode of div a0,a0,a1 is 0x02b54533 */
37 /* unsigned 32 bit division. opcode of divu a0,a0,a1 is 0x02b55533 */
42 * opcode of rem a0,a0,a1 is 0x02b56533
48 * opcode of remu a0,a0,a1 is 0x02b57533
/Zephyr-latest/tests/drivers/tee/optee/src/
Dmain.c32 typedef void (*smc_cb_t)(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3,
40 uint32_t a0; member
54 void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, unsigned long a3, in arm_smccc_smc() argument
58 if (a0 == OPTEE_SMC_CALLS_UID) { in arm_smccc_smc()
59 res->a0 = OPTEE_MSG_UID_0; in arm_smccc_smc()
66 if (a0 == OPTEE_SMC_EXCHANGE_CAPABILITIES) { in arm_smccc_smc()
70 if (a0 == OPTEE_SMC_GET_THREAD_COUNT) { in arm_smccc_smc()
75 t_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
78 wait_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
81 send_call.smc_cb(a0, a1, a2, a3, a4, a5, a6, a7, res); in arm_smccc_smc()
[all …]
/Zephyr-latest/drivers/interrupt_controller/
Dintc_nuclei_eclic.S42 csrrci a0, 0x345, MSTATUS_IEN
43 beqz a0, irq_done /* Check if original interrupt vanished. */
51 /* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
54 sub a0, a0, t0
56 slli a0, a0, (1)
57 add t0, t0, a0
59 /* Load argument in a0 register */
60 lw a0, 0(t0)
73 csrrci a0, 0x345, MSTATUS_IEN
74 bnez a0, irq_loop
/Zephyr-latest/arch/riscv/core/
Dpmp.S18 * void z_riscv_write_pmp_entries(unsigned int start, // a0
40 slli t1, a0, 4 /* 16-byte instruction blocks */
62 * a0 = a0 / RV_REGSIZE
66 srli a0, a0, RV_REGSHIFT
67 slli t1, a0, 4 /* 16-byte instruction blocks */
80 addi a0, a0, 1
82 beq a0, a1, pmpcfg_done
92 slli a0, a0, 2 /* 4-byte instruction blocks */
93 add t0, t0, a0
Dswitch.S50 lr sp, _thread_offset_to_sp(a0)
54 lr tp, _thread_offset_to_tls(a0)
58 /* Preserve a0 across following call. s0 is not yet restored. */
59 mv s0, a0
61 mv a0, s0
66 mv s0, a0
68 mv a0, s0
75 lb t0, _thread_offset_to_user_options(a0)
78 mv s0, a0
80 mv a0, s0
[all …]
Disr.S34 RV_E( op a0, __struct_arch_esf_a0_OFFSET(sp) );\
299 mv a0, sp
314 addi a0, sp, __struct_arch_esf_soc_context_OFFSET
326 * returned via register a0 (1: interrupt, 0 exception)
330 bnez a0, is_interrupt
370 lr a0, ___cpu_t_current_OFFSET(s0)
380 * to _Fault (via register a0).
384 mv a0, sp
424 lr a0, __struct_arch_esf_a0_OFFSET(sp)
433 lb t1, _thread_offset_to_exception_depth(a0)
[all …]
Dsemihost.c23 register unsigned long a0 __asm__ ("a0") = instr; in semihost_exec()
25 register long ret __asm__ ("a0"); in semihost_exec()
34 : "=r" (ret) : "r" (a0), "r" (a1) : "memory"); in semihost_exec()
Dfpu.S58 DO_FP_REGS(STORE, a0)
59 sw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
65 DO_FP_REGS(LOAD, a0)
66 lw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_s.h27 * A0-A15) to their ABI-defined spill regions on the stack.
35 * and repeats until all but the A0-A3 registers of the original frame
109 rur.fcr a0
110 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
111 rur.fsr a0
112 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
132 l32i.n a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
133 wur.fcr a0
134 l32i.n a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
135 wur.fsr a0
[all …]
/Zephyr-latest/soc/gd/gd32/gd32vf103/
Dentry.S17 la a0, __nuclei_start
20 bleu a1, a0, _start0800
22 bleu a1, a0, _start0800
23 la a0, _start0800
24 add a0, a0, a1
25 jr a0
/Zephyr-latest/drivers/tee/optee/
Doptee_smc.h76 * a0..a7 is used as register names in the descriptions below, on arm32
113 * Returns UUID in a0-4 in the same way as OPTEE_SMC_CALLS_UID
127 * Returns revision in a0-1 in the same way as OPTEE_SMC_CALLS_REVISION
139 * OPTEE_SMC_CALL_WITH_REGD_ARG in a0 there is one RPC struct optee_msg_arg
153 * a0 SMC Function ID, OPTEE_SMC_CALL_WITH_ARG or OPTEE_SMC_CALL_WITH_RPC_ARG
162 * a0 SMC Function ID, OPTEE_SMC_CALL_WITH_REGD_ARG
171 * a0 Return value, OPTEE_SMC_RETURN_*
176 * a0 Return value, OPTEE_SMC_RETURN_ETHREAD_LIMIT
181 * a0 Return value, OPTEE_SMC_RETURN_IS_RPC(val)
213 * a0 SMC Function ID, OPTEE_SMC_GET_SHM_CONFIG
[all …]
/Zephyr-latest/include/zephyr/arch/arm64/
Darm-smccc.h12 * @a0-a7 result values from registers 0 to 7
15 unsigned long a0; member
36 * @param a0 function identifier
40 void arm_smccc_hvc(unsigned long a0, unsigned long a1,
49 * @param a0 function identifier
53 void arm_smccc_smc(unsigned long a0, unsigned long a1,
/Zephyr-latest/soc/intel/intel_adsp/ace/
Dboot.c27 " movi a0, 0x4002f\n\t"
28 " wsr a0, PS\n\t"
29 " movi a0, 0\n\t"
30 " wsr a0, WINDOWBASE\n\t"
31 " movi a0, 1\n\t"
32 " wsr a0, WINDOWSTART\n\t"
/Zephyr-latest/soc/andestech/ae350/
Dsoc_irq.S28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
38 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
41 lw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-latest/soc/telink/tlsr/tlsr951x/
Dsoc_irq.S32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
42 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
45 lw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-latest/soc/wch/ch32v00x/
Dsoc_irq.S14 csrr a0, mcause
15 srli a0, a0, 31
/Zephyr-latest/soc/espressif/esp32c6/
Dsoc_irq.S15 csrr a0, mcause
16 srli a0, a0, 31
/Zephyr-latest/arch/mips/core/
Disr.S53 op a0, ESF_O(a0)(sp) ;\
114 /* a0 = ((cause & status) & CAUSE_IP_MASK) >> CAUSE_IP_SHIFT */
116 li a0, CAUSE_IP_MASK
117 and a0, a0, t1
118 srl a0, a0, CAUSE_IP_SHIFT
124 bnez a0, is_interrupt
127 move a0, sp
152 * Put 0 into a0: call z_mips_enter_irq() with ipending==0
155 move a0, zero
186 * function parameter since we put it in a0

12345678910>>...16