Lines Matching full:a0
27 * A0-A15) to their ABI-defined spill regions on the stack.
35 * and repeats until all but the A0-A3 registers of the original frame
109 rur.fcr a0
110 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
111 rur.fsr a0
112 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
132 l32i.n a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
133 wur.fcr a0
134 l32i.n a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
135 wur.fsr a0
159 * area pointed to by the current stack pointer. On exit, A0 will
167 rsr.sar a0
168 s32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
170 rsr.lbeg a0
171 s32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
172 rsr.lend a0
173 s32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
174 rsr.lcount a0
175 s32i a0, a1, ___xtensa_irq_bsa_t_lcount_OFFSET
177 rsr.exccause a0
178 s32i a0, a1, ___xtensa_irq_bsa_t_exccause_OFFSET
180 rsr.scompare1 a0
181 s32i a0, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET
185 rur.THREADPTR a0
186 s32i a0, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET
295 * (to save A0-A3) from registers. But they find their
349 * just before entering the call). On return A0/1 will be unchanged,
363 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
394 * the stack pointer decremented across a base save area, A0-A3 and
429 movi.n a0, 0
430 wur.THREADPTR a0
440 rsr.ps a0
442 and a0, a0, a3
444 or a0, a0, a3
445 wsr.ps a0
461 rsr.ps a0
463 and a0, a0, a3
464 bnez a0, _not_l1
465 rsr.ps a0
467 or a0, a0, a3
468 wsr.ps a0
482 rsil a0, 0xf
488 and a0, a0, a3
489 wsr.ZSR_EPS a0
490 wsr.ps a0
500 l32i a0, a3, \NEST_OFF
501 beqz a0, _switch_stacks_\@
504 addi a0, a0, 1
505 s32i a0, a3, \NEST_OFF
510 addi a0, a0, 1
511 s32i a0, a3, \NEST_OFF
521 rsil a0, XCHAL_NUM_INTLEVELS
525 l32i a0, a3, \NEST_OFF
526 addi a0, a0, -1
527 s32i a0, a3, \NEST_OFF
541 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
577 l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
591 * off the interrupted A0-A3 registers and the per-level PS/PC
639 wsr a0, ZSR_EXCCAUSE_SAVE
643 rsr a0, ZSR_DEPC_SAVE
644 beqz a0, _not_triple_fault
666 rsr a0, ZSR_EXCCAUSE_SAVE
670 rsr.exccause a0
672 xsr a0, ZSR_EXCCAUSE_SAVE
679 s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
689 rsr.ps a0
702 and a0, a0, a2
703 s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
705 rsr.eps\LVL a0
706 s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
709 rsr.epc\LVL a0
710 s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
737 l32r a0, _handle_excint_imm\LVL
738 jx a0