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/Zephyr-Core-3.5.0/include/zephyr/arch/riscv/
Dsyscall.h44 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke6()
53 : "+r" (a0) in arch_syscall_invoke6()
57 return a0; in arch_syscall_invoke6()
65 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke5()
73 : "+r" (a0) in arch_syscall_invoke5()
76 return a0; in arch_syscall_invoke5()
83 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke4()
90 : "+r" (a0) in arch_syscall_invoke4()
93 return a0; in arch_syscall_invoke4()
100 register unsigned long a0 __asm__ ("a0") = arg1; in arch_syscall_invoke3()
[all …]
/Zephyr-Core-3.5.0/soc/riscv/openisa_rv32m1/
Dsoc_irq.S25 csrr a0, mcause
26 srli a0, a0, 31
30 * With a0 == irq_num, this is equivalent to:
35 * that's calling us requires that a0 still contain irq_num
45 sll t1, t1, a0
65 sw t0, __soc_esf_t_lpstart0_OFFSET(a0)
66 sw t1, __soc_esf_t_lpend0_OFFSET(a0)
67 sw t2, __soc_esf_t_lpcount0_OFFSET(a0)
71 sw t0, __soc_esf_t_lpstart1_OFFSET(a0)
72 sw t1, __soc_esf_t_lpend1_OFFSET(a0)
[all …]
/Zephyr-Core-3.5.0/arch/xtensa/core/
Dxtensa-asm2-util.S18 * (so you have to save off A0, but no other registers need to be
154 l32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
155 wsr a0, ZSR_EPC
156 l32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
157 wsr a0, ZSR_EPS
163 l32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
164 wsr a0, SAR
166 l32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
167 wsr a0, LBEG
168 l32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
[all …]
Dwindow_vectors.S30 * all the registers from call[i+1]'s window. In particular, a0 and a1 must be
47 * a0-a3 are registers to be saved;
56 s32e a0, a5, -16 /* save a0 to call[j+1]'s stack frame */
69 * a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
78 l32e a0, a5, -16 /* restore a0 from call[i+1]'s stack frame */
86 * "free". All interruptee's regs are intact except a0 which is saved
100 rsr a0, WINDOWBASE /* grab WINDOWBASE before rotw changes it */
101 rotw -1 /* WINDOWBASE goes to a4, new a0-a3 are scratch */
105 rsr a4, ZSR_ALLOCA /* restore original a0 (now in a4) */
112 rotw -1 /* original a0 goes to a8 */
[all …]
Dcrt1.S72 * Keep a0 zero. It is used to initialize a few things.
79 movi a0, 0 /* keep this register zero. */
151 /* Clear a0 again as possible CALLX to __memmap_init changed it. */
152 movi a0, 0
160 * a0 = 0
176 s32i a0, a8, 0 /* clear 4 bytes to make len multiple of 8 */
179 s32i a0, a8, 0 /* clear 8 bytes to make len multiple of 16 */
180 s32i a0, a8, 4
184 s32i a0, a8, 0 /* clear 16 bytes at a time... */
185 s32i a0, a8, 4
[all …]
DREADME-WINDOWS.rst13 visible as A0-A15.
15 The first quad (A0-A3) is pointed to by a special register called
18 (respectively) A0-A3, A4-A7, A8-A11, and A12-A15.
24 A0).
31 the top two bits of the return address placed in A0.
39 top two bits from the return address in A0 and subtracts that value
61 being brought into A0-A3 (i.e. the new WINDOWBASE) has a set bit
86 The spill area for a single frame's A0-A3 registers is not in its own
101 to write a function using only A0-A3 and CALL4 calls and ignore higher
103 the top of the stack frame, immediately below the parent call's A0-A3
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/it8xxx2/
D__arithmetic.S31 /* signed 32 bit multiplication. opcode of mul a0,a0,a1 is 0x02b50533 */
34 /* signed 32 bit division. opcode of div a0,a0,a1 is 0x02b54533 */
37 /* unsigned 32 bit division. opcode of divu a0,a0,a1 is 0x02b55533 */
42 * opcode of rem a0,a0,a1 is 0x02b56533
48 * opcode of remu a0,a0,a1 is 0x02b57533
/Zephyr-Core-3.5.0/arch/riscv/core/
Dswitch.S50 lr sp, _thread_offset_to_sp(a0)
54 lr tp, _thread_offset_to_tls(a0)
58 /* Preserve a0 across following call. s0 is not yet restored. */
59 mv s0, a0
61 mv a0, s0
66 mv s0, a0
68 mv a0, s0
75 lb t0, _thread_offset_to_user_options(a0)
78 mv s0, a0
80 mv a0, s0
[all …]
Dpmp.S18 * void z_riscv_write_pmp_entries(unsigned int start, // a0
40 slli t1, a0, 4 /* 16-byte instruction blocks */
62 * a0 = a0 / RV_REGSIZE
66 srli a0, a0, RV_REGSHIFT
67 slli t1, a0, 4 /* 16-byte instruction blocks */
80 addi a0, a0, 1
82 beq a0, a1, pmpcfg_done
92 slli a0, a0, 2 /* 4-byte instruction blocks */
93 add t0, t0, a0
Disr.S33 RV_E( op a0, __z_arch_esf_t_a0_OFFSET(sp) );\
244 mv a0, sp
259 addi a0, sp, __z_arch_esf_t_soc_context_OFFSET
271 * returned via register a0 (1: interrupt, 0 exception)
275 /* If a0 != 0, jump to is_interrupt */
276 bnez a0, is_interrupt
306 * to _Fault (via register a0).
310 mv a0, sp
350 lr a0, __z_arch_esf_t_a0_OFFSET(sp)
357 li a0, 3
[all …]
Dsemihost.c23 register unsigned long a0 __asm__ ("a0") = instr; in semihost_exec()
25 register long ret __asm__ ("a0"); in semihost_exec()
34 : "=r" (ret) : "r" (a0), "r" (a1) : "memory"); in semihost_exec()
Dfpu.S58 DO_FP_REGS(STORE, a0)
59 sw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
65 DO_FP_REGS(LOAD, a0)
66 lw t0, __z_riscv_fp_context_t_fcsr_OFFSET(a0)
/Zephyr-Core-3.5.0/arch/xtensa/include/
Dxtensa-asm2-s.h23 * A0-A15) to their ABI-defined spill regions on the stack.
31 * and repeats until all but the A0-A3 registers of the original frame
105 rur.fcr a0
106 s32i a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
107 rur.fsr a0
108 s32i a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
128 l32i.n a0, a1, ___xtensa_irq_bsa_t_fcr_OFFSET
129 wur.fcr a0
130 l32i.n a0, a1, ___xtensa_irq_bsa_t_fsr_OFFSET
131 wur.fsr a0
[all …]
Dxtensa-asm2-context.h21 * SP-16 Caller A0 spill slot /
26 * SP-32 Saved A0
84 * Note that only A0-A3 are saved here. High registers
128 uintptr_t a0; member
162 * Interrupt stack frame containing A0 - A15.
188 * Interrupt stack frame containing A0 - A11.
209 * Interrupt stack frame containing A0 - A7.
225 * Interrupt stack frame containing A0 - A3.
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/gd32vf103/
Dentry.S16 la a0, __nuclei_start
19 bleu a1, a0, _start0800
21 bleu a1, a0, _start0800
22 la a0, _start0800
23 add a0, a0, a1
24 jr a0
/Zephyr-Core-3.5.0/include/zephyr/arch/arm64/
Darm-smccc.h12 * @a0-a7 result values from registers 0 to 7
15 unsigned long a0; member
36 * @param a0 function identifier
40 void arm_smccc_hvc(unsigned long a0, unsigned long a1,
49 * @param a0 function identifier
53 void arm_smccc_smc(unsigned long a0, unsigned long a1,
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/ace/
Dboot.c27 " movi a0, 0x4002f\n\t"
28 " wsr a0, PS\n\t"
29 " movi a0, 0\n\t"
30 " wsr a0, WINDOWBASE\n\t"
31 " movi a0, 1\n\t"
32 " wsr a0, WINDOWSTART\n\t"
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/andes_v5/
Dsoc_irq.S28 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
31 sw t1, __soc_esf_t_ucode_OFFSET(a0)
38 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
41 lw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/telink_b91/
Dsoc_irq.S32 sw t0, __soc_esf_t_mxstatus_OFFSET(a0)
35 sw t1, __soc_esf_t_ucode_OFFSET(a0)
42 lw t0, __soc_esf_t_mxstatus_OFFSET(a0)
45 lw t1, __soc_esf_t_ucode_OFFSET(a0)
/Zephyr-Core-3.5.0/soc/riscv/riscv-privileged/common/
Dsoc_irq.S25 * Exception number is given as parameter via register a0.
30 sll t0, t1, a0
55 addi a0, x0, 0
57 addi a0, a0, 1
/Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/
Dsoc_irq.S22 * Exception number is given as parameter via register a0.
43 csrr a0, mcause
44 srli a0, a0, 31
/Zephyr-Core-3.5.0/soc/riscv/espressif_esp32/esp32c3/
Dsoc_irq.S15 csrr a0, mcause
16 srli a0, a0, 31
/Zephyr-Core-3.5.0/arch/mips/core/
Disr.S53 op a0, ESF_O(a0)(sp) ;\
113 /* a0 = ((cause & status) & CAUSE_IP_MASK) >> CAUSE_IP_SHIFT */
115 li a0, CAUSE_IP_MASK
116 and a0, a0, t1
117 srl a0, a0, CAUSE_IP_SHIFT
123 bnez a0, is_interrupt
126 move a0, sp
151 * Put 0 into a0: call z_mips_enter_irq() with ipending==0
154 move a0, zero
185 * function parameter since we put it in a0
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Darduino-nano-header-r3.yaml12 signals labeled from A0 through A7, as well a digital signal D13. The
17 correspond to A0 through A7, as depicted below.
30 9 D9 A0/D14 14
/Zephyr-Core-3.5.0/soc/xtensa/intel_adsp/common/
Dmultiprocessing.c70 " movi a0, 0x4002f \n\t" /* WOE | UM | INTLEVEL(max) */
71 " wsr a0, PS \n\t"
72 " movi a0, 0 \n\t"
73 " wsr a0, WINDOWBASE \n\t"
74 " movi a0, 1 \n\t"
75 " wsr a0, WINDOWSTART \n\t"

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