1 /* Copyright(c) 2021 Intel Corporation. All rights reserved. 2 * SPDX-License-Identifier: Apache-2.0 3 */ 4 5 6 #include <stddef.h> 7 #include <stdint.h> 8 9 #include <zephyr/devicetree.h> 10 #include <zephyr/kernel.h> 11 #include <zephyr/init.h> 12 #include <soc.h> 13 #include <zephyr/cache.h> 14 #include <adsp_shim.h> 15 #include <adsp_memory.h> 16 #include <cpu_init.h> 17 #include "manifest.h" 18 19 #ifdef CONFIG_PM 20 #ifdef CONFIG_ADSP_IMR_CONTEXT_SAVE 21 #define STRINGIFY_MACRO(x) Z_STRINGIFY(x) 22 #define IMRSTACK STRINGIFY_MACRO(IMR_BOOT_LDR_MANIFEST_BASE) 23 __asm__(".section .imr.boot_entry_d3_restore, \"x\"\n\t" 24 ".align 4\n\t" 25 ".global boot_entry_d3_restore\n\t" 26 "boot_entry_d3_restore:\n\t" 27 " movi a0, 0x4002f\n\t" 28 " wsr a0, PS\n\t" 29 " movi a0, 0\n\t" 30 " wsr a0, WINDOWBASE\n\t" 31 " movi a0, 1\n\t" 32 " wsr a0, WINDOWSTART\n\t" 33 " rsync\n\t" 34 " movi a1, " IMRSTACK"\n\t" 35 " call4 boot_d3_restore\n\t"); 36 37 boot_d3_restore(void)38__imr void boot_d3_restore(void) 39 { 40 41 cpu_early_init(); 42 43 #ifdef CONFIG_ADSP_DISABLE_L2CACHE_AT_BOOT 44 ADSP_L2PCFG_REG = 0; 45 #endif 46 47 #ifdef RESET_MEMORY_HOLE 48 /* reset memory hole */ 49 CAVS_SHIM.l2mecs = 0; 50 #endif 51 extern void hp_sram_init(uint32_t memory_size); 52 hp_sram_init(L2_SRAM_SIZE); 53 54 extern void lp_sram_init(void); 55 lp_sram_init(); 56 57 extern void pm_state_imr_restore(void); 58 pm_state_imr_restore(); 59 } 60 #endif /* CONFIG_ADSP_IMR_CONTEXT_SAVE */ 61 #endif /* CONFIG_PM */ 62
