1/*
2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7/*
8 * common interrupt management code for riscv SOCs supporting the riscv
9 * privileged architecture specification
10 */
11#include <zephyr/kernel_structs.h>
12#include <offsets.h>
13#include <zephyr/toolchain.h>
14#include <zephyr/linker/sections.h>
15#include <soc.h>
16
17/*
18 * __soc_handle_irq is defined as .weak to allow re-implementation by
19 * SOCs that do not truly follow the riscv privilege specification.
20 */
21WTEXT(__soc_handle_irq)
22
23/*
24 * SOC-specific function to handle pending IRQ number generating the interrupt.
25 * Exception number is given as parameter via register a0.
26 */
27SECTION_FUNC(exception.other, __soc_handle_irq)
28	/* Clear exception number from CSR mip register */
29	li t1, 1
30	sll t0, t1, a0
31	csrrc t1, mip, t0
32
33	/* Return */
34	ret
35
36/*
37 * __soc_is_irq is defined as .weak to allow re-implementation by
38 * SOCs that do not truly follow the riscv privilege specification.
39 */
40WTEXT(__soc_is_irq)
41
42/*
43 * SOC-specific function to determine if the exception is the result of a
44 * an interrupt or an exception
45 * return 1 (interrupt) or 0 (exception)
46 *
47 */
48SECTION_FUNC(exception.other, __soc_is_irq)
49	/* Read mcause and check if interrupt bit is set */
50	csrr t0, mcause
51	li t1, SOC_MCAUSE_IRQ_MASK
52	and t0, t0, t1
53
54	/* If interrupt bit is not set, return with 0 */
55	addi a0, x0, 0
56	beqz t0, not_interrupt
57	addi a0, a0, 1
58
59not_interrupt:
60	/* return */
61	ret
62