| /Zephyr-latest/samples/boards/st/power_mgmt/suspend_to_ram/boards/ |
| D | nucleo_wba55cg.overlay | 16 min-residency-us = <500000>;
17 exit-latency-us = <50>;
20 min-residency-us = <1000000>;
21 exit-latency-us = <100>;
24 min-residency-us = <2000000>;
25 exit-latency-us = <1000>;
32 io-channels = <&adc4 8>;
45 channel@8 {
46 reg = <8>;
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| /Zephyr-latest/drivers/sensor/apds9960/ |
| D | Kconfig | 55 bool "8x"
82 bool "4us"
85 bool "8us"
88 bool "16us"
91 bool "32us"
116 default 8
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/lll/ |
| D | lll_df_types.h | 7 /* @brief Max supported CTE length in 8us units */
9 /* @brief Min supported CTE length in 8us units */
21 /* @brief Macro to convert length of CTE to [us] */
22 #define CTE_LEN_US(n) ((n) * 8U)
43 uint8_t cte_length:6; /* Length of CTE in 8us units */
50 /* BT 5.1 Vol 6, Part B, Section 2.5.4 reference period is sampled with 1us
51 * spacing. Thus we may have 8 IQ samples from reference period.
53 #define IQ_SAMPLE_REF_CNT 8
55 * If 1us sampling slots are supported maximum number of IQ samples in single CTE
56 * is 74 (sample spacing is 2us). If it is not supported maximum number of IQ
[all …]
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| /Zephyr-latest/subsys/bluetooth/controller/ |
| D | Kconfig.df | 55 bool "Reception of CTE with 1us sampling slots"
60 during CTE reception with 1us sampling slots.
65 bool "Support for 1us antenna switch slots"
69 Enable support for 1us antenna switching slots. This antenna switching
212 int "CTE sampling offset relative for PHY 1M and 1US samples spacing"
219 is 1 us. Decreasing the offset beyond the trigger of the AoA/AoD procedure will have
223 int "CTE sampling offset relative for PHY 1M and 1US samples spacing"
230 is 1 us. Decreasing the offset beyond the trigger of the AoA/AoD procedure will have
235 int "CTE sampling offset relative for PHY 1M and 2US samples spacing"
242 is 2 us. Decreasing the offset beyond the trigger of the AoA/AoD procedure will have
[all …]
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| /Zephyr-latest/dts/bindings/fpga/ |
| D | lattice,ice40-fpga-base.yaml | 25 creset-delay-us:
31 to 1us.
32 config-delay-us:
37 The datasheet specifies a minimum of 1200us, which is the default.
40 default: 8
43 The datasheet specifies 8 dummy cycles, which is the default.
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| /Zephyr-latest/samples/boards/ti/cc13x2_cc26x2/system_off/src/ |
| D | ext_flash.c | 15 #define DIO8_PIN 8
32 for (i = 0; i < 8; i++) { in CC1352R1_LAUNCHXL_sendExtFlashByte()
42 * 3 cycles per loop: 8 loops @ 48 Mhz = 0.5 us. in CC1352R1_LAUNCHXL_sendExtFlashByte()
44 CPUdelay(8); in CC1352R1_LAUNCHXL_sendExtFlashByte()
51 * Keep CS high at least 40 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
52 * 3 cycles per loop: 700 loops @ 48 Mhz ~= 44 us in CC1352R1_LAUNCHXL_sendExtFlashByte()
64 * least 20 ns and ten wait at least 35 us. in CC1352R1_LAUNCHXL_wakeUpExtFlash()
72 /* 3 cycles per loop: 560 loops @ 48 Mhz ~= 35 us */ in CC1352R1_LAUNCHXL_wakeUpExtFlash()
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| /Zephyr-latest/dts/bindings/tach/ |
| D | ene,kb1200-tach.yaml | 19 sample-time-us:
24 - 8
28 sampling time of tachometer. Please notice that it must be 2/8/16/64 us.
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| /Zephyr-latest/subsys/net/l2/ethernet/gptp/ |
| D | Kconfig | 53 bool "1us"
55 bool "2.5us"
57 bool "10us"
59 bool "25us"
61 bool "100us"
63 bool "250us"
177 default 8
180 Announce message. Each array element takes 8 bytes. If this value
181 is set to 8, then 8 * 8 = 64 bytes of memory is used.
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| /Zephyr-latest/dts/bindings/w1/ |
| D | adi,max32-w1.yaml | 54 approximately 5us (micro second), 15us, and 7us, respectively.
58 and the time-slot recovery times out to approximately 8us, 22us, and 14us, respectively.
|
| /Zephyr-latest/boards/st/stm32g081b_eval/ |
| D | stm32g081b_eval.dts | 34 gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
52 gpios = <&gpioc 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
94 mul-n = <8>;
182 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
183 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
213 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
214 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
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| /Zephyr-latest/boards/st/stm32g071b_disco/ |
| D | stm32g071b_disco.dts | 9 #include <st/g0/stm32g071r(6-8-b)tx-pinctrl.dtsi>
31 gpios = <&gpiod 8 GPIO_ACTIVE_HIGH>;
111 mul-n = <8>;
148 vbus-conversion-time-us = <1100>;
149 vshunt-conversion-time-us = <1100>;
178 * tTransitionWindow = 1.687 uS * 8 = 13.5 uS
179 * tInterFrameGap = 1.687 uS * 17 = 28.68 uS
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| /Zephyr-latest/samples/drivers/jesd216/ |
| D | README.rst | 40 Support 1-1-2: instr 3Bh, 0 mode clocks, 8 waits
41 Support 1-1-4: instr 6Bh, 0 mode clocks, 8 waits
49 Byte program: type 32 + 1 * B us, max 192 + 6 * B us
50 Page program: typ 896 us, max 5376 us
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| /Zephyr-latest/soc/st/stm32/stm32f4x/ |
| D | power.c | 36 /* According to datasheet (DS11139 Rev 8,Table 38.), wakeup with regulator in in pm_state_set()
37 * low-power mode takes typically 8us, max 13us more time than with the main in pm_state_set()
38 * regulator. We are using RTC as a wakeup source, which has a tick 62,5us. in pm_state_set()
|
| /Zephyr-latest/drivers/led_strip/ |
| D | tlc59731.c | 13 * TLC59731 is a 3-Channel, 8-Bit, PWM LED Driver
18 * between 1.67us and 50us. We want to go as fast as possible, but
19 * delays under 1us don't work very well, so we settle on 5us for the
25 * A one is represented by an additional pulse between 275ns and 2.5us
28 * full 1us. After the pulse, we wait an additional T_CYCLE_1 to complete
44 #define TLC59731_DELAY 0x01 /* us */
45 #define TLC59731_T_CYCLE_0 0x04 /* us */
46 #define TLC59731_T_CYCLE_1 0x01 /* us */
48 #define TLC59731_T_H1 (8 * TLC59731_T_CYCLE_0)
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| /Zephyr-latest/drivers/w1/ |
| D | w1_zephyr_serial.c | 35 * RST: t_RSTL=520us; t_slot=1041us
36 * DATA: t_low1=8.68us; t_low0=78.1us; t_slot=86.8us
44 * RST: t_RSTL=52.1us; t_slot=86.8us
45 * DATA: t_low1=1.0us; t_low0=9.0us; t_slot=10.0us
101 uint8_t byte_representation[8]; in serial_tx_rx_byte()
103 for (int i = 0; i < 8; ++i) { in serial_tx_rx_byte()
114 8, CONFIG_W1_ZEPHYR_SERIAL_BIT_TIMEOUT) < 0) { in serial_tx_rx_byte()
119 for (int i = 0; i < 8; ++i) { in serial_tx_rx_byte()
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| /Zephyr-latest/dts/bindings/led_strip/ |
| D | ws2812.yaml | 26 For the control signal (waveform) each bit is described with a 1.2 us pulse:
33 The latch/reset delay is 250 us and it must be set using the reset-delay
42 default: 8
45 latched the signal. If omitted, a default value of 8 microseconds is used.
48 6 microseconds is enough. The default is set to 8 microseconds just to be
|
| /Zephyr-latest/drivers/ethernet/dwc_xgmac/ |
| D | Kconfig | 31 int "A timeout value in us to check software reset status"
40 int "XGMAC interrupt polling interval in us"
44 XGMAC interrupt polling interval in us
48 default 8
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| /Zephyr-latest/subsys/bluetooth/controller/ll_sw/ |
| D | lll_conn_iso.h | 14 uint64_t max_pdu:8; /* Maximum PDU size */
15 uint64_t ft:8; /* Flush timeout (FT) */
36 uint32_t offset; /* Offset of CIS from start of CIG in us */
37 uint32_t sub_interval; /* Interval between subevents in us */
108 uint32_t window_widening_periodic_us_frac; /* Widening in us fractions
111 uint32_t window_widening_prepare_us_frac; /* Widening in us fractions
115 * us fractions for active
118 uint32_t window_widening_max_us; /* Maximum widening in us */
|
| /Zephyr-latest/include/zephyr/bluetooth/ |
| D | cs.h | 38 #define BT_LE_CS_CHANNEL_BIT_GET(chmap, bit) (((chmap)[(bit) / 8] >> ((bit) % 8)) & 1)
48 ((chmap)[(bit) / 8] = ((chmap)[(bit) / 8] & ~BIT((bit) % 8)) | ((val) << ((bit) % 8)))
165 * | 8 | A1 A4 A2 A3 |
223 /** CS Test Override 8 CS_SYNC Payload Pattern */
268 * Range: 1250us to 4s
296 * - 10 us
297 * - 20 us
298 * - 30 us
299 * - 40 us
300 * - 50 us
[all …]
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| /Zephyr-latest/tests/bsim/bluetooth/ll/throughput/src/ |
| D | main.c | 25 * Single Tx time, 2M PHY = 1064 us
26 * tIFS = 150 us
27 * Single Tx duration = 1214 us
28 * Full duplex Tx-Rx duration = 2428 us
29 * Implementation dependent event overhead = 340 us
30 * Max. incomplete PDU time = 1064 us
31 * Max. radio idle time per 1 second = (1064 + 340) * 20 = 28080 us
34 * Throughput = 400 * 244 * 8 = 780800 bps
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| /Zephyr-latest/tests/subsys/logging/log_benchmark/src/ |
| D | main.c | 115 TEST_LOG_CAPACITY(8, total_cnt, 1); in ZTEST()
132 DBG_PRINT("%d arguments message logged in %u cycles (%u us). " \
151 TEST_LOG_MESSAGE_STORE_NO_OVERFLOW(8, total_cyc, total_msg); in run_log_message_store_time_no_overwrite()
155 PRINT("%sAverage logging a message: %u cycles (%u us)\n", in run_log_message_store_time_no_overwrite()
177 DBG_PRINT("%d arguments message logged in %u cycles (%u us). " \
196 TEST_LOG_MESSAGE_STORE_OVERFLOW(8, 50, total_cyc, total_msg); in ZTEST()
200 PRINT("Average overwrite logging a message: %u cycles (%u us)\n", in ZTEST()
219 int repeat = 8; in ZTEST()
226 uint32_t us = k_cyc_to_us_ceil32(cyc); in ZTEST() local
228 PRINT("%slogging with transient string %u cycles (%u us).", in ZTEST()
[all …]
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| /Zephyr-latest/dts/bindings/input/ |
| D | st,stmpe811.yaml | 41 panel-driver-settling-time-us:
56 As a general rule, 1-5 nF capacitors require around 500 us settling time, and 5-10 nF need
60 touch-detect-delay-us:
84 - 8
101 - 8
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| /Zephyr-latest/samples/drivers/auxdisplay/boards/ |
| D | esp_wrover_kit.overlay | 10 ngpios = <8>;
22 enable-line-rise-delay-us = <1000>;
23 enable-line-fall-delay-us = <500>;
|
| /Zephyr-latest/drivers/dma/ |
| D | dma_pl330.h | 29 * b011 = 8 bytes
60 * TIMEOUT value of 100000us is kept to cover all possible data
61 * transfer sizes, with lesser time out value(10us) DMA channel
62 * appears to be busy on FPGA/Emul environment. Ideally 100000us
74 #define DMA_CH_SHIFT 8
88 #define CC_SRCPRI_SHIFT 8
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| /Zephyr-latest/dts/bindings/auxdisplay/ |
| D | hit,hd44780.yaml | 17 description: Operating mode of display, 8-bit or 4 for 4-bit mode
20 - 8
41 contain 8 entries ascending from DB0 to DB7, for 4-bit interface
80 clear-command-delay-us:
84 Delay time (in us) to wait after issuing a clear command before sending
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