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/Zephyr-latest/drivers/pinctrl/
Dpinctrl_b91.c4 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/pinctrl/b91-pinctrl.h>
17 * gpio_en: PORT_A[0-7]
18 * gpio_en + 1*8: PORT_B[0-7]
19 * gpio_en + 2*8: PORT_C[0-7]
20 * gpio_en + 3*8: PORT_D[0-7]
21 * gpio_en + 4*8: PORT_E[0-7]
22 * gpio_en + 5*8: PORT_F[0-7]
24 #define reg_gpio_en(pin) (*(volatile uint8_t *)((uint32_t)DT_INST_REG_ADDR_BY_NAME(0, gpio_en) + \ argument
25 ((pin >> 8) * 8)))
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Dpinctrl_eos_s3.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/pinctrl/quicklogic-eos-s3-pinctrl.h>
25 #define PAD_DRIVE_STRENGTH_BIT0 8
34 static int pinctrl_eos_s3_input_selection(uint32_t pin, uint32_t sel_reg) in pinctrl_eos_s3_input_selection() argument
39 return -EINVAL; in pinctrl_eos_s3_input_selection()
42 *reg = pin; in pinctrl_eos_s3_input_selection()
50 static int pinctrl_eos_s3_set(uint32_t pin, uint32_t func) in pinctrl_eos_s3_set() argument
54 if (pin > IO_MUX_REG_MAX_OFFSET) { in pinctrl_eos_s3_set()
55 return -EINVAL; in pinctrl_eos_s3_set()
57 reg += pin; in pinctrl_eos_s3_set()
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/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dgecko-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
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Dgecko-pinctrl-s1.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
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Dnumicro-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
14 #define NUMICRO_PORT_SHIFT 8U
18 * @brief Pin configuration configuration bit field.
22 * - mfp [ 0 : 3 ]
23 * - pin [ 4 : 7 ]
24 * - port [ 8 : 11 ]
27 * @param pin Pin (0..15)
28 * @param mfp Multi-function value (0..15)
30 #define NUMICRO_PINMUX(port, pin, mfp) \ argument
31 (((((port) - 'A') & NUMICRO_PORT_MASK) << NUMICRO_PORT_SHIFT) | \
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Dmax32-pinctrl.h2 * Copyright (c) 2023-2024 Analog Devices, Inc.
4 * SPDX-License-Identifier: Apache-2.0
11 * @brief Pin modes
21 * @brief Mode, port, pin shift number
27 #define MAX32_PIN_SHIFT 8U
31 * @brief Pin configuration bit field.
35 * - mode [ 0 : 3 ]
36 * - port [ 4 : 7 ]
37 * - pin [ 8 : 15 ]
40 * @param pin Pin (0..31)
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/Zephyr-latest/dts/bindings/sensor/
Dst,iis328dq-common.yaml3 # SPDX-License-Identifier: Apache-2.0
5 include: sensor-device.yaml
8 int1-gpios:
9 type: phandle-array
11 INT_1 pin
13 This pin defaults to active high when produced by the sensor. The property value should ensure
16 int2-gpios:
17 type: phandle-array
19 INT_2 pin
21 This pin defaults to active high when produced by the sensor. The property value should ensure
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Dnxp,fxls8974-common.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: FXLS8974 3-axis accelerometer sensor
6 include: sensor-device.yaml
9 reset-gpios:
10 type: phandle-array
12 RST pin
13 This pin defaults to active high when consumed by the sensor.
17 int1-gpios:
18 type: phandle-array
20 INT1 pin
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Dst,ism330dhcx-common.yaml2 # SPDX-License-Identifier: Apache-2.0
5 When setting the accel-odr and gyro-odr properties in a .dts or .dtsi file you may include
9 #include <zephyr/dt-bindings/sensor/ism330dhcx.h>
14 accel-odr = <ISM330DHCX_DT_ODR_104Hz>;
15 gyro-odr = <ISM330DHCX_DT_ODR_104Hz>;
18 include: sensor-device.yaml
21 drdy-gpios:
22 type: phandle-array
24 DRDY gpio pin
26 This pin defaults to active high when produced by the sensor.
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Dnxp,fxos8700-common.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: FXOS8700 6-axis accelerometer/magnetometer sensor
6 include: sensor-device.yaml
9 reset-gpios:
10 type: phandle-array
12 RST pin
13 This pin defaults to active high when consumed by the sensor.
17 int1-gpios:
18 type: phandle-array
20 INT1 pin
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/Zephyr-latest/dts/bindings/gpio/
Dparticle-gen3-header.yaml2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
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Dnxp,pca_series.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Base binding for PCA series I2C-based GPIO expander
6 include: [gpio-controller.yaml, i2c-device.yaml]
21 # (b) PCAL6534 has 34 GPIO pins in 4x 8-bit port and 1x
22 # 2-bit port. This driver only support 4x 8-bit port.
25 reset-gpios:
26 type: phandle-array
28 Reset GPIO pin (active-low)
29 Left blank if the device does not have reset pin
30 or the pin is not connected in your application.
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Darduino-header-r3.yaml3 # SPDX-License-Identifier: Apache-2.0
11 Proceeding counter-clockwise:
12 * An 8-pin Power Supply header. No pins on this header are exposed
14 * A 6-pin Analog Input header. This has analog input signals
16 * An 8-pin header (opposite Analog Input). This has digital input
18 * A 10-pin header (opposite Power Supply). This has six additional
29 AREF -
30 GND -
31 - N/C D13 19
32 - IOREF D12 18
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Dnxp,pcf857x.yaml2 # 2023 Amrith Venkat Kesavamoorthi <amrith@mr-beam.org>
4 # SPDX-License-Identifier: Apache-2.0
6 description: PCF857x 8/16-bit I2C-based I/O expander
10 include: [i2c-device.yaml, gpio-controller.yaml]
16 - 8
17 - 16
19 int-gpios:
20 type: phandle-array
22 GPIO connected to the controller INT pin. This pin is active-low.
24 "#gpio-cells":
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Dnxp,lcd-8080.yaml2 # SPDX-License-Identifier: Apache-2.0
5 compatible: "nxp,lcd-8080"
8 GPIO pins exposed on NXP LCD 8080 interface (e.g., used on LCD-PAR-035 panel).
9 These pins are exposed on a 32 pin connector. The pins have the
12 Pin Number Usage
20 8 LCD touch controller I2C SDA
24 12 LCD 8080 interface D/C pin
25 13 LCD 8080 interface CS pin
26 14 LCD 8080 interface WR pin
27 15 LCD 8080 interface RD pin
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/Zephyr-latest/dts/bindings/pinctrl/
Dti,cc13xx-cc26xx-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
7 Device pin configuration should be placed in the child nodes of this node.
8 Populate the 'pinmux' field with a pair consisting of a pin number and its IO
18 All device pin configurations should be placed in child nodes of the
22 supported standard pin properties:
24 - bias-disable: Disable pull-up/down.
25 - bias-pull-down: Enable pull-down resistor.
26 - bias-pull-up: Enable pull-up resistor.
27 - drive-open-drain: Output driver is open-drain.
28 - drive-open-drain: Output driver is open-source.
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Drenesas,smartbond-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 The SmartBond pin controller is a singleton node responsible for controlling
6 pin function selection and pin properties, such as routing a UART RX to pin
7 P1.8 and enabling the pullup resistor on that pin.
16 All device pin configurations should be placed in child nodes of the
19 /* You can put this in places like a board-pinctrl.dtsi file in
24 #include <dt-bindings/pinctrl/smartbond-pinctrl.h>
36 /* route UART RX to P0.8 and enable pull-up */
37 pinmux = <SMARTBOND_PINMUX(UART_RX, 0, 8)>;
38 bias-pull-up;
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Dadi,max32-pinctrl.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
5 MAX32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` are default pin configurations.
10 compatible: "adi,max32-pinctrl"
19 child-binding:
24 - name: pincfg-node.yaml
25 property-allowlist:
26 - bias-disable
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/Zephyr-latest/drivers/interrupt_controller/
Dintc_sam0_eic.c4 * SPDX-License-Identifier: Apache-2.0
16 uint8_t pin : 5; member
34 while (EIC->SYNCBUSY.reg) { in wait_synchronization()
37 while (EIC->STATUS.bit.SYNCBUSY) { in wait_synchronization()
45 EIC->CTRLA.bit.ENABLE = on; in set_eic_enable()
47 EIC->CTRL.bit.ENABLE = on; in set_eic_enable()
53 struct sam0_eic_data *const dev_data = dev->data; in sam0_eic_isr()
54 uint16_t bits = EIC->INTFLAG.reg; in sam0_eic_isr()
58 EIC->INTFLAG.reg = bits; in sam0_eic_isr()
68 line_index = 8; in sam0_eic_isr()
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/Zephyr-latest/drivers/pinctrl/renesas/rcar/
Dpfc_rcar.c2 * Copyright (c) 2021-2023 IoT.bzh
4 * SPDX-License-Identifier: Apache-2.0
43 /* POC Control Register can control IO voltage level that is supplied to the pin */
53 * 24/4 mA or 24/8 mA.
57 (size == 2 ? PFC_RCAR_DRIVE_MAX / 4 : PFC_RCAR_DRIVE_MAX / 8)
68 /* Set the pin either in gpio or peripheral */
70 uint16_t pin, bool peripheral) in pfc_rcar_set_gpsr() argument
74 uint8_t bank = pin / 32; in pfc_rcar_set_gpsr()
79 uint8_t bit = pin % 32; in pfc_rcar_set_gpsr()
95 uint16_t reg_offs = PFC_RCAR_IPSR + rcar_func->bank * sizeof(uint32_t); in pfc_rcar_set_ipsr()
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/Zephyr-latest/soc/intel/alder_lake/
Dsoc_gpio.h2 * Copyright (c) 2021-2023, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
36 (pin_offset % 8) ? \
38 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
40 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
42 #define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
44 #define GPIO_RAW_PIN(pin, pin_offset) pin argument
47 (cfg->group_index * 0x4)
50 (cfg->group_index * 0x4)
/Zephyr-latest/soc/intel/elkhart_lake/
Dsoc_gpio.h4 * SPDX-License-Identifier: Apache-2.0
36 (pin_offset % 8) ? \
38 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) : \
40 (((pin_offset / 8) + (raw_pin / 8)) * 0x4); \
42 #define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
44 #define GPIO_RAW_PIN(pin, pin_offset) pin argument
47 (cfg->group_index * 0x4)
50 (cfg->group_index * 0x4)
/Zephyr-latest/dts/arm/infineon/cat1a/legacy/
Dpsoc6.dtsi3 * Copyright (c) 2020-2021, ATL Electronics
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include "psoc6-pinctrl.dtsi"
15 #address-cells = <1>;
16 #size-cells = <0>;
20 compatible = "arm,cortex-m0+";
25 compatible = "arm,cortex-m4f";
30 flash-controller@40250000 {
31 compatible = "cypress,psoc6-flash-controller";
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/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dstm32-gpio.h4 * SPDX-License-Identifier: Apache-2.0
13 * The driver flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
16 * - Bit 8: Configure a GPIO pin to power on the system after Poweroff.
23 * Configures a GPIO pin to power on the system after Poweroff.
24 * This flag is reserved to GPIO pins that are associated with wake-up pins
25 * in STM32 PWR devicetree node, through the property "wkup-gpios".
27 #define STM32_GPIO_WKUP (1 << 8)
Dnordic-nrf-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nRF-specific GPIO Flags
11 * @defgroup gpio_interface_nrf nRF-specific GPIO Flags
20 * Standard (S) or High (H) drive modes can be applied to both pin levels, 0 or
21 * 1. High drive mode will increase current capabilities of the pin (refer to
24 * When the pin is configured to operate in open-drain mode (wired-and), the
26 * Similarly, when the pin is configured to operate in open-source mode
27 * (wired-or), the drive mode can only be set for the 1 level
30 * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
33 * - Bit 8: Drive mode for '0' (0=Standard, 1=High)
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