Home
last modified time | relevance | path

Searched +full:8 +full:- +full:9 (Results 1 – 25 of 1043) sorted by relevance

12345678910>>...42

/Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/
Dservice_a_1.c4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
50 '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1', '1', '1',
53 '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9',
54 '9', '9', '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '2',
57 '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9',
61 '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9', '0', '0',
[all …]
/Zephyr-latest/dts/bindings/clock/
Dnuvoton,npcx-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
Dnuvoton,npcm-pcc.yaml2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
/Zephyr-latest/boards/we/proteus3ev/
Dwe_proteus3ev_nrf52840-pinctrl.dtsi4 psels = <NRF_PSEL(UART_TX, 1, 8)>,
8 psels = <NRF_PSEL(UART_RX, 1, 9)>,
10 bias-pull-up;
16 psels = <NRF_PSEL(UART_TX, 1, 8)>,
17 <NRF_PSEL(UART_RX, 1, 9)>,
20 low-power-enable;
26 psels = <NRF_PSEL(TWIM_SDA, 1, 9)>,
27 <NRF_PSEL(TWIM_SCL, 1, 8)>;
33 psels = <NRF_PSEL(TWIM_SDA, 1, 9)>,
34 <NRF_PSEL(TWIM_SCL, 1, 8)>;
[all …]
/Zephyr-latest/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
/Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/img/
Dsymbiflow.svg1 …-2.6.6-5 1.7-7.4 1.1-2.3 2.7-4.4 4.8-6.1 2.1-1.8 4.6-3.2 7.6-4.3 3-1.1 6.4-1.6 10.2-1.6 3.7 0 7 .5…
/Zephyr-latest/scripts/
Dcheckstack.pl8 # s390 port and big speedup by Arnd Bergmann <arnd@bergmann-dalldorf.de>
20 # objdump -d vmlinux | scripts/checkstack.pl [arch]
41 $arch = `uname -m`;
45 $x = "[0-9a-f]"; # hex character
46 $xs = "[0-9a-f ]"; # hex character or space
49 #ffffffc0006325cc: a9bb7bfd stp x29, x30, [sp,#-80]!
50 $re = qr/^.*stp.*sp,\#-([0-9]{1,8})\]\!/o;
53 $re = qr/.*sub.*sp, sp, #(([0-9]{2}|[3-9])[0-9]{2})/o;
57 $re = qr/^.*sub.*sp.*,([0-9]{1,8})/o;
62 $re = qr/^.*[as][du][db] \$(0x$x{1,8}),\%(e|r)sp$/o;
[all …]
/Zephyr-latest/boards/nordic/nrf5340_audio_dk/
Dnrf5340_audio_dk_nrf5340_cpunet-pinctrl.dtsi3 * SPDX-License-Identifier: Apache-2.0
9 psels = <NRF_PSEL(UART_TX, 1, 9)>,
13 psels = <NRF_PSEL(UART_RX, 1, 8)>,
15 bias-pull-up;
21 psels = <NRF_PSEL(UART_TX, 1, 9)>,
22 <NRF_PSEL(UART_RX, 1, 8)>,
25 low-power-enable;
31 psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
33 <NRF_PSEL(SPIM_MOSI, 0, 9)>;
39 psels = <NRF_PSEL(SPIM_SCK, 0, 8)>,
[all …]
/Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-lvol-ctrl-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 /* Common Low-Voltage level configurations in npcx family */
8 #include <nuvoton/npcx/npcx-lvol-ctrl-map.dtsi>
10 /* Specific Low-Voltage level configurations in npcx4 series */
12 def-lvol-conf-list {
13 compatible = "nuvoton,npcx-lvolctrl-conf";
15 /* Low-Voltage IO Control 1 */
20 /* Low-Voltage IO Control 2 */
25 /* Low-Voltage IO Control 5 */
39 /* Low-Voltage IO Control 6 */
[all …]
/Zephyr-latest/tests/lib/cmsis_dsp/filtering/src/
Dmisc_f16.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
17 #define REL_ERROR_THRESH (1.0e-4)
18 #define ABS_ERROR_THRESH (1.0e-3)
20 #define REL_ERROR_THRESH_LD (1.0e-3)
21 #define ABS_ERROR_THRESH_LD (1.0e-3)
60 DEFINE_CORRELATE_TEST(4, 8);
65 DEFINE_CORRELATE_TEST(5, 8);
70 DEFINE_CORRELATE_TEST(6, 8);
72 DEFINE_CORRELATE_TEST(9, 1);
[all …]
Dmisc_f32.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
17 #define REL_ERROR_THRESH (1.0e-6)
18 #define ABS_ERROR_THRESH (1.0e-5)
19 #define REL_ERROR_THRESH_LD (1.0e-6)
20 #define ABS_ERROR_THRESH_LD (1.0e-6)
31 * refer to the CMSIS-DSP bug ARM-software/CMSIS-DSP#59. in test_arm_correlate_f32()
38 output = output_buf + 8; in test_arm_correlate_f32()
68 DEFINE_CORRELATE_TEST(4, 8);
73 DEFINE_CORRELATE_TEST(5, 8);
[all …]
Dmisc_q31.c3 * Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
5 * SPDX-License-Identifier: Apache-2.0
30 * refer to the CMSIS-DSP bug ARM-software/CMSIS-DSP#59. in test_arm_correlate_q31()
37 output = output_buf + 8; in test_arm_correlate_q31()
64 DEFINE_CORRELATE_TEST(4, 8);
69 DEFINE_CORRELATE_TEST(5, 8);
74 DEFINE_CORRELATE_TEST(6, 8);
76 DEFINE_CORRELATE_TEST(9, 1);
77 DEFINE_CORRELATE_TEST(9, 2);
78 DEFINE_CORRELATE_TEST(9, 3);
[all …]
/Zephyr-latest/soc/intel/apollo_lake/
Dsoc_gpio.h2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
31 #define APL_GPIO_8 8
32 #define APL_GPIO_9 9
65 #define APL_GPIO_40 8
66 #define APL_GPIO_41 9
99 #define APL_GPIO_CNV_BRI_RSP 8
100 #define APL_GPIO_CNV_RGI_DT 9
115 #define APL_GPIO_195 8
116 #define APL_GPIO_196 9
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77951.h4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
21 #define PIN_D8 RCAR_GP_PIN(0, 8)
22 #define PIN_D9 RCAR_GP_PIN(0, 9)
37 #define PIN_A8 RCAR_GP_PIN(1, 8)
38 #define PIN_A9 RCAR_GP_PIN(1, 9)
66 #define PIN_PWM2_A RCAR_GP_PIN(2, 8)
67 #define PIN_AVB_MDC RCAR_GP_PIN(2, 9)
81 #define PIN_SD1_DATA0 RCAR_GP_PIN(3, 8)
[all …]
Dpinctrl-r8a77961.h3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
22 #define PIN_D8 RCAR_GP_PIN(0, 8)
23 #define PIN_D9 RCAR_GP_PIN(0, 9)
38 #define PIN_A8 RCAR_GP_PIN(1, 8)
39 #define PIN_A9 RCAR_GP_PIN(1, 9)
67 #define PIN_PWM2_A RCAR_GP_PIN(2, 8)
68 #define PIN_AVB_MDC RCAR_GP_PIN(2, 9)
[all …]
/Zephyr-latest/tests/drivers/adc/adc_api/boards/
Dmax32672evkit.overlay4 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc 8>, <&adc 9>;
16 pinctrl-0 = <&ain8_p0_16 &ain9_p0_17>;
17 pinctrl-names = "default";
18 #address-cells = <1>;
19 #size-cells = <0>;
21 channel@8 {
22 reg = <8>;
25 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
29 channel@9 {
[all …]
Dmax32672fthr.overlay4 * SPDX-License-Identifier: Apache-2.0
10 io-channels = <&adc 8>, <&adc 9>;
16 pinctrl-0 = <&ain8_p0_16 &ain9_p0_17>;
17 pinctrl-names = "default";
18 #address-cells = <1>;
19 #size-cells = <0>;
21 channel@8 {
22 reg = <8>;
25 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
29 channel@9 {
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dambiq-apollo4-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
27 #define OBSBUS0_P0 APOLLO4_PINMUX(0, 8)
28 #define VCMPO_P0 APOLLO4_PINMUX(0, 9)
38 #define OBSBUS1_P1 APOLLO4_PINMUX(1, 8)
39 #define VCMPO_P1 APOLLO4_PINMUX(1, 9)
50 #define OBSBUS2_P2 APOLLO4_PINMUX(2, 8)
51 #define VCMPO_P2 APOLLO4_PINMUX(2, 9)
62 #define OBSBUS3_P3 APOLLO4_PINMUX(3, 8)
73 #define OBSBUS4_P4 APOLLO4_PINMUX(4, 8)
74 #define I2S0_SDIN_P4 APOLLO4_PINMUX(4, 9)
[all …]
Desp32c2-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
29 #define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
31 #define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
58 #define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
60 #define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
87 #define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
89 #define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
116 #define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
118 #define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
145 #define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
[all …]
/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
40 IPC_EVENT_BIT(8) | \
41 IPC_EVENT_BIT(9) | \
60 [8] = BIT(8),
61 [9] = BIT(9),
78 [8] = BIT(8),
79 [9] = BIT(9),
/Zephyr-latest/include/zephyr/dt-bindings/espi/
Dnpcx_espi.h4 * SPDX-License-Identifier: Apache-2.0
10 * Encode virtual wire information into a 16-bit unsigned.
12 * group = bits[11:8], Group number for VWEVMS or VWEVSM
16 (((dir & 0x1) << 12) + ((group & 0xf) << 8) + (index & 0xff))
20 #define ESPI_NPCX_VW_EX_GROUP_NUM(e) (((e) >> 8) & 0xf)
32 #define NPCX_VWEVMS8 8
33 #define NPCX_VWEVMS9 9
47 #define NPCX_VWEVSM8 8
48 #define NPCX_VWEVSM9 9
60 #define NPCX_VWGPSM8 8
[all …]
/Zephyr-latest/samples/tfm_integration/psa_crypto/
DREADME.rst1 .. zephyr:code-sample:: tfm_psa_crypto
2 :name: TF-M PSA crypto
8 This TF-M integration example demonstrates how to use the PSA crypto API in
10 this example also demonstrates certain TF-M features that are covered as part
15 Trusted Firmware (TF-M) Platform Security Architecture (PSA) APIs
17 non-secure processing environment.
20 handle secure TF-M API calls and responses.
22 The sample prints test info to the console either as a single-thread or
23 multi-thread application.
26 https://www.psacertified.org/security-certification/psa-certified-level-1/
[all …]
/Zephyr-latest/samples/subsys/zbus/runtime_obs_registration/
Dsample.yaml7 - qemu_x86
14 - "I: System started"
15 - "I: Activating filter"
16 - "I: Deactivating filter"
17 - "I: Bypass filter"
18 - "I: Disable bypass filter"
19 - "I: >-- Raw data fetched"
20 - "I: -|- Filtering data"
21 - "I: --> Consuming data: Acc x=0, y=0, z=0"
22 - "I: --> Consuming data: Acc x=2, y=2, z=2"
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dnordic-npm2100-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM2100-specific GPIO Flags
11 * @defgroup gpio_interface_npm2100 nPM2100-specific GPIO Flags
13 * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
16 * - Bit 8: Drive strength (0=1mA, 1=6mA)
17 * - Bit 9: Debounce (0=OFF, 1=ON)
35 #define NPM2100_GPIO_DRIVE_NORMAL (0U << 8U)
37 #define NPM2100_GPIO_DRIVE_HIGH (1U << 8U)
53 #define NPM2100_GPIO_DEBOUNCE_OFF (0U << 9U)
55 #define NPM2100_GPIO_DEBOUNCE_ON (1U << 9U)
Dnordic-npm6001-gpio.h4 * SPDX-License-Identifier: Apache-2.0
10 * @brief nPM6001-specific GPIO Flags
11 * @defgroup gpio_interface_npm6001 nPM6001-specific GPIO Flags
13 * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
16 * - Bit 8: Drive strength (0=NORMAL, 1=HIGH)
17 * - Bit 9: Input type (0=SCHMITT, 1=CMOS)
35 #define NPM6001_GPIO_DRIVE_NORMAL (0U << 8U)
37 #define NPM6001_GPIO_DRIVE_HIGH (1U << 8U)
53 #define NPM6001_GPIO_SENSE_SCHMITT (0U << 9U)
55 #define NPM6001_GPIO_SENSE_CMOS (1U << 9U)

12345678910>>...42