| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/ |
| D | service_a_1.c | 4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
46 '8', '9', '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
50 '9', '9', '9', '9', '0', '0', '0', '0', '0', '1', '1', '1', '1',
53 '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9',
54 '9', '9', '0', '0', '0', '0', '0', '1', '1', '1', '1', '1', '2',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
57 '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9',
[all …]
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| D | service_c_2_2.c | 4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
47 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '\0'
52 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
53 '8', '9', '9', '9', '\0'
57 '4', '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7',
58 '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9',
59 '9', '0', '0', '0', '0', '\0'
63 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8',
64 '8', '8', '8', '8', '9', '9', '9', '9', '9', '0', '0', '0', '0',
[all …]
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| D | service_c_2_3.c | 4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
47 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '\0'
52 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
53 '8', '9', '9', '9', '\0'
57 '4', '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7',
58 '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9',
59 '9', '0', '0', '0', '0', '\0'
63 '5', '5', '6', '6', '6', '6', '6', '7', '7', '7', '7', '7', '8',
64 '8', '8', '8', '8', '9', '9', '9', '9', '9', '0', '0', '0', '0',
[all …]
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcx-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
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| D | nuvoton,npcm-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(96)>; /* OFMCLK runs at 96MHz */
15 core-prescaler = <1>; /* CORE_CLK runs at 96MHz */
16 apb1-prescaler = <8>; /* APB1_CLK runs at 12MHz */
17 apb2-prescaler = <1>; /* APB2_CLK runs at 96MHz */
18 apb3-prescaler = <1>; /* APB3_CLK runs at 96MHz */
19 apb6-prescaler = <1>; /* APB6_CLK runs at 96MHz */
20 fiu-prescaler = <1>; /* FIU_CLK runs at 96MHz */
21 i3c-prescaler = <1>; /* I3C_CLK runs at 96MHz */
[all …]
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| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
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| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-lvol-ctrl-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Common Low-Voltage level configurations in npcx family */
8 #include <nuvoton/npcx/npcx-lvol-ctrl-map.dtsi>
10 /* Specific Low-Voltage level configurations in npcx4 series */
12 def-lvol-conf-list {
13 compatible = "nuvoton,npcx-lvolctrl-conf";
15 /* Low-Voltage IO Control 1 */
17 lvols = <&scfg 1 7>;
20 /* Low-Voltage IO Control 2 */
25 /* Low-Voltage IO Control 5 */
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| /Zephyr-latest/boards/renesas/ek_ra8d1/ |
| D | ek_ra8d1-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
11 drive-strength = "medium";
32 psels = <RA_PSEL(RA_PSEL_GPT1, 10, 7)>;
45 drive-strength = "high";
53 drive-strength = "medium";
64 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
65 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
66 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
67 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
68 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
[all …]
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| /Zephyr-latest/boards/nordic/nrf54h20dk/ |
| D | nrf54h20dk_nrf54h20-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
8 /omit-if-no-ref/ uart120_default: uart120_default {
10 psels = <NRF_PSEL(UART_TX, 7, 7)>;
14 bias-pull-up;
15 psels = <NRF_PSEL(UART_RX, 7, 4)>;
19 /omit-if-no-ref/ uart120_sleep: uart120_sleep {
21 low-power-enable;
22 psels = <NRF_PSEL(UART_TX, 7, 7)>,
23 <NRF_PSEL(UART_RX, 7, 4)>;
27 /omit-if-no-ref/ uart135_default: uart135_default {
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| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/img/ |
| D | symbiflow.svg | 1 …-2.6.6-5 1.7-7.4 1.1-2.3 2.7-4.4 4.8-6.1 2.1-1.8 4.6-3.2 7.6-4.3 3-1.1 6.4-1.6 10.2-1.6 3.7 0 7 .5…
|
| /Zephyr-latest/doc/connectivity/bluetooth/img/ |
| D | ble_cfg_dual.xml | 1 …-03-07T14:48:10.055Z" host="www.draw.io" agent="Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWeb…
|
| /Zephyr-latest/drivers/pm_cpu_ops/ |
| D | pm_cpu_ops_psci.h | 4 * SPDX-License-Identifier: Apache-2.0
31 #define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU PSCI_0_2_FN(7)
33 #define PSCI_0_2_FN_SYSTEM_RESET PSCI_0_2_FN(9)
38 #define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
39 #define PSCI_0_2_FN64_SYSTEM_RESET PSCI_0_2_FN(9)
54 #define PSCI_1_0_FN_MIGRATE_INFO_UP_CPU PSCI_1_0_FN(7)
56 #define PSCI_1_0_FN_SYSTEM_RESET PSCI_1_0_FN(9)
62 #define PSCI_1_0_FN64_MIGRATE_INFO_UP_CPU PSCI_1_0_FN64(7)
64 #define PSCI_1_0_FN64_SYSTEM_RESET PSCI_1_0_FN(9)
80 #define PSCI_1_1_FN_MIGRATE_INFO_UP_CPU PSCI_1_1_FN(7)
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| /Zephyr-latest/soc/intel/apollo_lake/ |
| D | soc_gpio.h | 2 * Copyright (c) 2018-2019, Intel Corporation
4 * SPDX-License-Identifier: Apache-2.0
30 #define APL_GPIO_7 7
32 #define APL_GPIO_9 9
64 #define APL_GPIO_39 7
66 #define APL_GPIO_41 9
98 #define APL_GPIO_CNV_BRI_DT 7
100 #define APL_GPIO_CNV_RGI_DT 9
114 #define APL_GPIO_194 7
116 #define APL_GPIO_196 9
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ambiq-apollo4-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
26 #define NCE0_P0 APOLLO4_PINMUX(0, 7)
28 #define VCMPO_P0 APOLLO4_PINMUX(0, 9)
37 #define NCE1_P1 APOLLO4_PINMUX(1, 7)
39 #define VCMPO_P1 APOLLO4_PINMUX(1, 9)
49 #define NCE2_P2 APOLLO4_PINMUX(2, 7)
51 #define VCMPO_P2 APOLLO4_PINMUX(2, 9)
61 #define NCE3_P3 APOLLO4_PINMUX(3, 7)
72 #define NCE4_P4 APOLLO4_PINMUX(4, 7)
74 #define I2S0_SDIN_P4 APOLLO4_PINMUX(4, 9)
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| D | esp32c2-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
27 #define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
31 #define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
56 #define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
60 #define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
85 #define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
89 #define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
114 #define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
118 #define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
143 #define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
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| D | ti-cc32xx-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77951.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
20 #define PIN_D7 RCAR_GP_PIN(0, 7)
22 #define PIN_D9 RCAR_GP_PIN(0, 9)
36 #define PIN_A7 RCAR_GP_PIN(1, 7)
38 #define PIN_A9 RCAR_GP_PIN(1, 9)
65 #define PIN_PWM1_A RCAR_GP_PIN(2, 7)
67 #define PIN_AVB_MDC RCAR_GP_PIN(2, 9)
80 #define PIN_SD1_CMD RCAR_GP_PIN(3, 7)
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| D | pinctrl-r8a77961.h | 3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
21 #define PIN_D7 RCAR_GP_PIN(0, 7)
23 #define PIN_D9 RCAR_GP_PIN(0, 9)
37 #define PIN_A7 RCAR_GP_PIN(1, 7)
39 #define PIN_A9 RCAR_GP_PIN(1, 9)
66 #define PIN_PWM1_A RCAR_GP_PIN(2, 7)
68 #define PIN_AVB_MDC RCAR_GP_PIN(2, 9)
[all …]
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| /Zephyr-latest/drivers/ipm/ |
| D | ipm_nrfx_ipc.h | 4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
39 IPC_EVENT_BIT(7) | \
41 IPC_EVENT_BIT(9) | \
59 [7] = BIT(7),
61 [9] = BIT(9),
77 [7] = BIT(7),
79 [9] = BIT(9),
|
| /Zephyr-latest/include/zephyr/dt-bindings/memory-controller/ |
| D | renesas,ra-sdram.h | 3 * SPDX-License-Identifier: Apache-2.0
15 #define SDRAM_TRAS_7CYCLES (7)
28 #define SDRAM_TRP_7CYCLES (7)
44 #define SDRAM_TREFW_7CYCLES (7)
46 #define SDRAM_TREFW_9CYCLES (9)
59 #define SDRAM_AUTO_REFREDSH_INTERVEL_7CYCLES (7)
61 #define SDRAM_AUTO_REFREDSH_INTERVEL_9CYCLES (9)
80 #define SDRAM_AUTO_REFREDSH_COUNT_7TIMES (7)
82 #define SDRAM_AUTO_REFREDSH_COUNT_9TIMES (9)
94 #define SDRAM_AUTO_PRECHARGE_CYCLE_7CYCLES (7)
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| /Zephyr-latest/samples/subsys/zbus/runtime_obs_registration/ |
| D | sample.yaml | 7 - qemu_x86
14 - "I: System started"
15 - "I: Activating filter"
16 - "I: Deactivating filter"
17 - "I: Bypass filter"
18 - "I: Disable bypass filter"
19 - "I: >-- Raw data fetched"
20 - "I: -|- Filtering data"
21 - "I: --> Consuming data: Acc x=0, y=0, z=0"
22 - "I: --> Consuming data: Acc x=2, y=2, z=2"
[all …]
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| /Zephyr-latest/samples/tfm_integration/psa_crypto/ |
| D | README.rst | 1 .. zephyr:code-sample:: tfm_psa_crypto
2 :name: TF-M PSA crypto
8 This TF-M integration example demonstrates how to use the PSA crypto API in
10 this example also demonstrates certain TF-M features that are covered as part
15 Trusted Firmware (TF-M) Platform Security Architecture (PSA) APIs
17 non-secure processing environment.
20 handle secure TF-M API calls and responses.
22 The sample prints test info to the console either as a single-thread or
23 multi-thread application.
26 https://www.psacertified.org/security-certification/psa-certified-level-1/
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| /Zephyr-latest/tests/bluetooth/qualification/ |
| D | ICS_Zephyr_Bluetooth_Controller_nrf52833dk_nrf52833.pts | 1 <?xml version="1.0" encoding="utf-8"?>
31 <table>9</table>
100 <row>7</row>
144 <row>7</row>
152 <row>9</row>
184 <row>7</row>
308 <row>7</row>
311 <table>7</table>
315 <table>7</table>
319 <table>7</table>
[all …]
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| /Zephyr-latest/boards/st/nucleo_c031c6/ |
| D | arduino_r3_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "arduino-header-r3";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 0 0>, /* A0 */
19 <6 0 &gpiob 7 0>, /* D0 */
20 <7 0 &gpiob 6 0>, /* D1 */
22 <9 0 &gpiob 3 0>, /* D3 */
27 <14 0 &gpioa 9 0>, /* D8 */
[all …]
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| /Zephyr-latest/boards/blues/swan_r5/ |
| D | feather_connector.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "adafruit-feather-header";
10 #gpio-cells = <2>;
11 gpio-map-mask = <0xffffffff 0xffffffc0>;
12 gpio-map-pass-thru = <0 0x3f>;
13 gpio-map = <0 0 &gpioa 3 0>, /* A0 */
20 <7 0 &gpioa 7 0>, /* MOSI */
22 <9 0 &gpioa 10 0>, /* RX */
23 <10 0 &gpioa 9 0>, /* TX */
25 <12 0 &gpiob 7 0>, /* SDA */
[all …]
|
