| /Zephyr-latest/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/ |
| D | service_a_1.c | 4 * SPDX-License-Identifier: Apache-2.0
9 * This code is auto-generated from the Excel Workbook
44 '3', '3', '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6',
45 '6', '6', '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8',
48 '4', '4', '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6',
49 '6', '6', '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9',
52 '4', '4', '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6',
53 '7', '7', '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9',
56 '4', '5', '5', '5', '5', '5', '6', '6', '6', '6', '6', '7', '7',
57 '7', '7', '7', '8', '8', '8', '8', '8', '9', '9', '9', '9', '9',
[all …]
|
| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx4/ |
| D | npcx4-miwus-wui-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Common Wake-Up Unit Input (WUI) mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-wui-map.dtsi>
10 /* Specific Wake-Up Unit Input (WUI) mapping configurations in npcx4 series */
13 npcx-miwus-wui-map {
14 compatible = "nuvoton,npcx-miwu-wui-map";
18 wui_ioe7: wui0-8-7 {
19 miwus = <&miwu0 7 7>; /* GPIOE7 */
24 wui_io13: wui1-2-3 {
29 wui_io66: wui1-7-6 {
[all …]
|
| D | npcx4-lvol-ctrl-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Common Low-Voltage level configurations in npcx family */
8 #include <nuvoton/npcx/npcx-lvol-ctrl-map.dtsi>
10 /* Specific Low-Voltage level configurations in npcx4 series */
12 def-lvol-conf-list {
13 compatible = "nuvoton,npcx-lvolctrl-conf";
15 /* Low-Voltage IO Control 1 */
17 lvols = <&scfg 1 7>;
20 /* Low-Voltage IO Control 2 */
22 lvols = <&scfg 2 6>;
[all …]
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| /Zephyr-latest/dts/arm/nuvoton/npcx/ |
| D | npcx-miwus-wui-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
9 npcx-miwus-wui-map {
10 compatible = "nuvoton,npcx-miwu-wui-map";
14 wui_io80: wui0-1-0 {
17 wui_io81: wui0-1-1 {
20 wui_io82: wui0-1-2 {
23 wui_io83: wui0-1-3 {
26 wui_io87: wui0-1-7 {
27 miwus = <&miwu0 0 7>; /* GPIO87 */
31 wui_io90: wui0-2-0 {
[all …]
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| /Zephyr-latest/tests/net/traffic_class/ |
| D | testcase.yaml | 3 - native_sim
4 - native_sim/native/64
6 - native_sim/native/64
8 - net
9 - traffic_class
13 - CONFIG_NET_TC_TX_COUNT=1
14 - CONFIG_NET_TC_RX_COUNT=1
17 - CONFIG_NET_TC_TX_COUNT=2
18 - CONFIG_NET_TC_RX_COUNT=2
21 - CONFIG_NET_TC_TX_COUNT=3
[all …]
|
| /Zephyr-latest/drivers/ieee802154/ |
| D | ieee802154_rf2xx_regs.h | 1 /* ieee802154_rf2xx_regs.h - ATMEL RF2XX transceiver registers */
6 * SPDX-License-Identifier: Apache-2.0
12 /*- Definitions ------------------------------------------------------------*/
27 #define RF2XX_RSSI_BPSK_20 -100
28 #define RF2XX_RSSI_BPSK_40 -99
29 #define RF2XX_RSSI_OQPSK_SIN_RC_100 -98
30 #define RF2XX_RSSI_OQPSK_SIN_250 -97
31 #define RF2XX_RSSI_OQPSK_RC_250 -97
33 /*- Types ------------------------------------------------------------------*/
96 #define RF2XX_CCA_DONE 7
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|
| /Zephyr-latest/samples/subsys/nvs/ |
| D | sample.yaml | 10 - nrf52dk/nrf52832
15 - "Id: 1, Address: 192.168.1.1"
16 - "Id: 2, Key: ff fe fd fc fb fa f9 f8"
17 - "Id: 3, Reboot_counter: (.*)"
18 - "Id: 4, Data: DATA"
19 - "Id: 5, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b \
22 56 57 58 59 5a 5b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 \
23 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f"
|
| /Zephyr-latest/include/zephyr/dt-bindings/clock/ |
| D | npcm_clock.h | 4 * SPDX-License-Identifier: Apache-2.0
16 #define NPCM_CLOCK_UART2 (NPCM_CLOCK_GROUP_OFFSET(0) + 6)
22 #define NPCM_CLOCK_MFT2 (NPCM_CLOCK_GROUP_OFFSET(1) + 6)
23 #define NPCM_CLOCK_MFT3 (NPCM_CLOCK_GROUP_OFFSET(1) + 7)
30 #define NPCM_CLOCK_PWM_G (NPCM_CLOCK_GROUP_OFFSET(2) + 6)
31 #define NPCM_CLOCK_PWM_H (NPCM_CLOCK_GROUP_OFFSET(2) + 7)
38 #define NPCM_CLOCK_GDMA (NPCM_CLOCK_GROUP_OFFSET(3) + 7)
45 #define NPCM_CLOCK_SPIP1 (NPCM_CLOCK_GROUP_OFFSET(4) + 7)
50 #define NPCM_CLOCK_DP80 (NPCM_CLOCK_GROUP_OFFSET(5) + 6)
51 #define NPCM_CLOCK_MSWC (NPCM_CLOCK_GROUP_OFFSET(5) + 7)
[all …]
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| /Zephyr-latest/boards/enjoydigital/litex_vexriscv/doc/img/ |
| D | symbiflow.svg | 1 …-2.6.6-5 1.7-7.4 1.1-2.3 2.7-4.4 4.8-6.1 2.1-1.8 4.6-3.2 7.6-4.3 3-1.1 6.4-1.6 10.2-1.6 3.7 0 7 .5…
|
| /Zephyr-latest/dts/arm/nuvoton/npcx/npcx9/ |
| D | npcx9-miwus-wui-map.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 /* Common Wake-Up Unit Input (WUI) mapping configurations in npcx family */
8 #include <nuvoton/npcx/npcx-miwus-wui-map.dtsi>
10 /* Specific Wake-Up Unit Input (WUI) mapping configurations in npcx9 series */
13 npcx-miwus-wui-map {
14 compatible = "nuvoton,npcx-miwu-wui-map";
18 wui_cr_sin2: wui0-1-6-2 {
19 miwus = <&miwu0 0 6>; /* CR_SIN2 */
23 wui_io66: wui1-7-6 {
24 miwus = <&miwu1 6 6>; /* GPIO66 */
[all …]
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| /Zephyr-latest/drivers/sensor/st/lsm6dsl/ |
| D | lsm6dsl.h | 1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
30 #define LSM6DSL_SHIFT_FUNC_CFG_EN 7
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
51 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_EN BIT(7)
52 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_EN 7
53 #define LSM6DSL_MASK_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY BIT(6)
54 #define LSM6DSL_SHIFT_FIFO_CTRL2_TIMER_PEDO_FIFO_DRDY 6
70 #define LSM6DSL_MASK_FIFO_CTRL4_STOP_ON_FTH BIT(7)
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/ |
| D | ti-cc32xx-pinctrl.h | 3 * SPDX-License-Identifier: Apache-2.0
10 * The whole TI CC32XX pin configuration information is encoded in a 32-bit
13 * - 31..22: Reserved
14 * - 21..16: Pin.
15 * - 15..10: Reserved.
16 * - 9: Pull-down flag.
17 * - 8: Pull-up flag.
18 * - 7..5: Drive strength.
19 * - 4: Enable open-drain flag.
20 * - 3..0: Configuration mode
[all …]
|
| D | ambiq-apollo4-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
25 #define CT0_P0 APOLLO4_PINMUX(0, 6)
26 #define NCE0_P0 APOLLO4_PINMUX(0, 7)
36 #define CT1_P1 APOLLO4_PINMUX(1, 6)
37 #define NCE1_P1 APOLLO4_PINMUX(1, 7)
48 #define CT2_P2 APOLLO4_PINMUX(2, 6)
49 #define NCE2_P2 APOLLO4_PINMUX(2, 7)
60 #define CT3_P3 APOLLO4_PINMUX(3, 6)
61 #define NCE3_P3 APOLLO4_PINMUX(3, 7)
71 #define CT4_P4 APOLLO4_PINMUX(4, 6)
[all …]
|
| D | ambiq-apollo3-pinctrl.h | 4 * SPDX-License-Identifier: Apache-2.0
24 #define NCE0_P0 APOLLO3_PINMUX(0, 7)
30 #define NCE1_P1 APOLLO3_PINMUX(1, 7)
36 #define NCE2_P2 APOLLO3_PINMUX(2, 7)
42 #define TRIG1_P3 APOLLO3_PINMUX(3, 6)
43 #define I2SWCLK_P3 APOLLO3_PINMUX(3, 7)
49 #define CTIM17_P4 APOLLO3_PINMUX(4, 6)
50 #define MSPI0_2_P4 APOLLO3_PINMUX(4, 7)
55 #define CT8_P5 APOLLO3_PINMUX(5, 7)
56 #define M0SDAWIR3_P6 APOLLO3_PINMUX(6, 0)
[all …]
|
| /Zephyr-latest/drivers/charger/ |
| D | bq24190.h | 4 * SPDX-License-Identifier: Apache-2.0
12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
13 #define BQ24190_REG_ISC_EN_HIZ_SHIFT 7
14 #define BQ24190_REG_ISC_VINDPM_MASK GENMASK(6, 3)
18 /* Power-On Configuration */
20 #define BQ24190_REG_POC_RESET_MASK BIT(7)
21 #define BQ24190_REG_POC_RESET_SHIFT 7
23 #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6)
24 #define BQ24190_REG_POC_WDT_RESET_SHIFT 6
40 #define BQ24190_REG_CCC_ICHG_MASK GENMASK(7, 2)
[all …]
|
| /Zephyr-latest/boards/nxp/lpcxpresso55s69/ |
| D | board.c | 3 * SPDX-License-Identifier: Apache-2.0
18 * Flexcomm 6 and 7 are connected to codec on board, and shared signal in lpcxpresso_55s69_board_init()
23 /* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_board_init()
24 SYSCTL->SHAREDCTRLSET[0] = SYSCTL_SHAREDCTRLSET_SHAREDSCKSEL(7) | in lpcxpresso_55s69_board_init()
25 SYSCTL_SHAREDCTRLSET_SHAREDWSSEL(7); in lpcxpresso_55s69_board_init()
28 /* Select Data in from Transmit I2S - Flexcomm 7 */ in lpcxpresso_55s69_board_init()
29 SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_SHAREDDATASEL(7); in lpcxpresso_55s69_board_init()
30 /* Enable Transmit I2S - Flexcomm 7 for Shared Data Out */ in lpcxpresso_55s69_board_init()
31 SYSCTL->SHAREDCTRLSET[0] |= SYSCTL_SHAREDCTRLSET_FC7DATAOUTEN(1); in lpcxpresso_55s69_board_init()
34 /* Set Receive I2S - Flexcomm 6 SCK, WS from shared signal set 0 */ in lpcxpresso_55s69_board_init()
[all …]
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| /Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/ |
| D | lsm9ds0_gyro.h | 1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
24 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_DR 6
43 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_INT1 BIT(7)
44 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_INT1 7
45 #define LSM9DS0_GYRO_MASK_CTRL_REG3_G_I1_BOOT BIT(6)
46 #define LSM9DS0_GYRO_SHIFT_CTRL_REG3_G_I1_BOOT 6
61 #define LSM9DS0_GYRO_MASK_CTRL_REG4_G_BDU BIT(7)
62 #define LSM9DS0_GYRO_SHIFT_CTRL_REG4_G_BDU 7
[all …]
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| /Zephyr-latest/include/zephyr/dt-bindings/pinctrl/renesas/ |
| D | pinctrl-r8a77961.h | 3 * Copyright (c) 2023-2024 EPAM Systems
5 * SPDX-License-Identifier: Apache-2.0
10 #include "pinctrl-rcar-common.h"
13 #define PIN_NONE -1
20 #define PIN_D6 RCAR_GP_PIN(0, 6)
21 #define PIN_D7 RCAR_GP_PIN(0, 7)
36 #define PIN_A6 RCAR_GP_PIN(1, 6)
37 #define PIN_A7 RCAR_GP_PIN(1, 7)
65 #define PIN_PWM0 RCAR_GP_PIN(2, 6)
66 #define PIN_PWM1_A RCAR_GP_PIN(2, 7)
[all …]
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| D | pinctrl-r8a77951.h | 4 * SPDX-License-Identifier: Apache-2.0
9 #include "pinctrl-rcar-common.h"
12 #define PIN_NONE -1
19 #define PIN_D6 RCAR_GP_PIN(0, 6)
20 #define PIN_D7 RCAR_GP_PIN(0, 7)
35 #define PIN_A6 RCAR_GP_PIN(1, 6)
36 #define PIN_A7 RCAR_GP_PIN(1, 7)
64 #define PIN_PWM0 RCAR_GP_PIN(2, 6)
65 #define PIN_PWM1_A RCAR_GP_PIN(2, 7)
79 #define PIN_SD1_CLK RCAR_GP_PIN(3, 6)
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| /Zephyr-latest/drivers/sensor/st/lsm9ds0_mfd/ |
| D | lsm9ds0_mfd.h | 1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer
8 * SPDX-License-Identifier: Apache-2.0
22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
23 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZYXMOR 7
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
25 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_ZMOR 6
50 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_XMIEN BIT(7)
51 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_XMIEN 7
52 #define LSM9DS0_MFD_MASK_INT_CTRL_REG_M_YMIEN BIT(6)
53 #define LSM9DS0_MFD_SHIFT_INT_CTRL_REG_M_YMIEN 6
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| /Zephyr-latest/dts/bindings/clock/ |
| D | nuvoton,npcx-pcc.yaml | 2 # SPDX-License-Identifier: Apache-2.0
8 High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
14 clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
15 core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
16 apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
17 apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
18 apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
21 compatible: "nuvoton,npcx-pcc"
23 include: [clock-controller.yaml, base.yaml]
29 clock-frequency:
[all …]
|
| /Zephyr-latest/samples/subsys/fs/zms/ |
| D | README.rst | 1 .. zephyr:code-sample:: zms
3 :relevant-api: zms_high_level_api
40 .. zephyr-app-commands::
41 :zephyr-app: samples/subsys/fs/zms
51 .. code-block:: console
53 *** Booting Zephyr OS build v3.7.0-2383-g624f75400242 ***
72 …Id: 3, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f …
73 …b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b …
91 …Id: 3, Longarray: 0 1 2 3 4 5 6 7 8 9 a b c d e f 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f …
92 …b 5c 5d 5e 5f 60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f 70 71 72 73 74 75 76 77 78 79 7a 7b …
|
| /Zephyr-latest/dts/arm/infineon/cat3/xmc/ |
| D | xmc4500_F100x1024-intc.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <zephyr/dt-bindings/interrupt-controller/infineon-xmc4xxx-intc.h>
9 port-line-mapping = <
14 XMC4XXX_INTC_SET_LINE_MAP(2, 0, 7, 0) /* ERU0_ETL0_INPUTB_P2_0 XMC_ERU_ETL_INPUT_B3 */
15 XMC4XXX_INTC_SET_LINE_MAP(2, 4, 6, 0) /* ERU0_ETL0_INPUTB_P2_4 XMC_ERU_ETL_INPUT_B2 */
20 XMC4XXX_INTC_SET_LINE_MAP(2, 2, 6, 1) /* ERU0_ETL1_INPUTB_P2_2 XMC_ERU_ETL_INPUT_B2 */
21 XMC4XXX_INTC_SET_LINE_MAP(2, 6, 7, 1) /* ERU0_ETL1_INPUTB_P2_6 XMC_ERU_ETL_INPUT_B3 */
24 XMC4XXX_INTC_SET_LINE_MAP(0, 12, 6, 2) /* ERU0_ETL2_INPUTB_P0_12 XMC_ERU_ETL_INPUT_B2 */
25 XMC4XXX_INTC_SET_LINE_MAP(0, 4, 7, 2) /* ERU0_ETL2_INPUTB_P0_4 XMC_ERU_ETL_INPUT_B3 */
26 XMC4XXX_INTC_SET_LINE_MAP(0, 7, 5, 2) /* ERU0_ETL2_INPUTB_P0_7 XMC_ERU_ETL_INPUT_B1 */
[all …]
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| /Zephyr-latest/samples/modules/cmsis_dsp/moving_average/ |
| D | sample.yaml | 7 - samples
9 - qemu_cortex_m0
10 - native_sim
12 - cmsis-dsp
17 - "Input\\[00\\]: 0 0 0 0 0 0 0 0 0 0 | Output\\[00\\]: 0.00"
18 - "Input\\[01\\]: 0 0 0 0 0 0 0 0 0 1 | Output\\[01\\]: 0.10"
19 - "Input\\[02\\]: 0 0 0 0 0 0 0 0 1 2 | Output\\[02\\]: 0.30"
20 - "Input\\[03\\]: 0 0 0 0 0 0 0 1 2 3 | Output\\[03\\]: 0.60"
21 - "Input\\[04\\]: 0 0 0 0 0 0 1 2 3 4 | Output\\[04\\]: 1.00"
22 - "Input\\[05\\]: 0 0 0 0 0 1 2 3 4 5 | Output\\[05\\]: 1.50"
[all …]
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| /Zephyr-latest/boards/renesas/ek_ra8d1/ |
| D | ek_ra8d1-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
11 drive-strength = "medium";
32 psels = <RA_PSEL(RA_PSEL_GPT1, 10, 7)>;
36 psels = <RA_PSEL(RA_PSEL_GPT1, 10, 6)>;
45 drive-strength = "high";
53 drive-strength = "medium";
63 <RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
64 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
65 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
66 <RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
[all …]
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