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/Zephyr-latest/include/zephyr/bluetooth/
Dbyteorder.h8 * SPDX-License-Identifier: Apache-2.0
26 /** @brief Encode 16-bit value into array values in little-endian format.
28 * Helper macro to encode 16-bit values into comma separated values.
32 * @param _v 16-bit integer in host endianness.
34 * @return The comma separated values for the 16-bit value.
40 /** @brief Encode 24-bit value into array values in little-endian format.
42 * Helper macro to encode 24-bit values into comma separated values.
46 * @param _v 24-bit integer in host endianness.
48 * @return The comma separated values for the 24-bit value.
54 /** @brief Encode 32-bit value into array values in little-endian format.
[all …]
/Zephyr-latest/include/zephyr/sys/
Dbyteorder.h6 * Copyright (c) 2015-2016, Intel Corporation.
8 * SPDX-License-Identifier: Apache-2.0
32 #define BSWAP_48(x) ((uint64_t) ((((x) >> 40) & 0xff) | \
37 (((x) & 0xff) << 40)))
39 (((x) >> 40) & 0xff00) | \
44 (((x) & 0xff00) << 40) | \
48 * @brief Convert 16-bit integer from little-endian to host endianness.
50 * @param val 16-bit integer in little-endian format.
52 * @return 16-bit integer in host endianness.
56 * @brief Convert 16-bit integer from host endianness to little-endian.
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/Zephyr-latest/arch/arm64/core/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
18 This option signifies the use of a CPU of the Cortex-A family.
31 This option signifies the use of a CPU of the Cortex-R 64-bit family.
38 This option signifies the use of a Cortex-A53 CPU
45 This option signifies the use of a Cortex-A55 CPU
52 This option signifies the use of a Cortex-A57 CPU
59 This option signifies the use of a Cortex-A72 CPU
66 This option signifies the use of a Cortex-A76 CPU
73 This option signifies the use of a Cortex-A76 and A55 big little CPU cluster
80 This option signifies the use of a Cortex-R82 CPU
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/Zephyr-latest/include/zephyr/
Dnet_buf.h8 * SPDX-License-Identifier: Apache-2.0
84 * The main use of this is for scenarios where the meta-data of the normal
123 * @return Pointer to stack-allocated net_buf_simple object.
145 if (!buf->__buf) { in net_buf_simple_init()
146 buf->__buf = (uint8_t *)buf + sizeof(*buf); in net_buf_simple_init()
149 buf->data = buf->__buf + reserve_head; in net_buf_simple_init()
150 buf->len = 0U; in net_buf_simple_init()
174 buf->len = 0U; in net_buf_simple_reset()
175 buf->data = buf->__buf; in net_buf_simple_reset()
220 * @brief Add (8-bit) byte at the end of the buffer
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/lll/
Dlll_tim_internal.h2 * Copyright (c) 2018-2019 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
19 case BIT(0): in addr_us_get()
20 return 40; in addr_us_get()
21 case BIT(1): in addr_us_get()
23 case BIT(2): in addr_us_get()
/Zephyr-latest/dts/bindings/w1/
Dadi,max32-w1.yaml1 # Copyright (c) 2023-2024 Analog Devices, Inc.
2 # SPDX-License-Identifier: Apache-2.0
4 description: ADI MAX32xxx MCUs 1-Wire Master
6 include: [w1-master.yaml, pinctrl-device.yaml]
8 compatible: "adi,max32-w1"
20 pinctrl-0:
23 pinctrl-names:
26 internal-pullup:
32 0 - Internal pullup disabled.
33 1 - Internal pullup enabled.
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/Zephyr-latest/samples/bluetooth/channel_sounding/include/
Dcs_test_params.h4 * SPDX-License-Identifier: Apache-2.0
32 params.t_pm_time = 40; in test_params_get()
41 params.override_config = BIT(2) | BIT(5); in test_params_get()
46 for (uint8_t i = 40; i < 75; i++) { in test_params_get()
/Zephyr-latest/drivers/sensor/st/lis3mdl/
Dlis3mdl.h4 * SPDX-License-Identifier: Apache-2.0
21 #define LIS3MDL_TEMP_EN_MASK BIT(7)
23 #define LIS3MDL_OM_MASK (BIT(6) | BIT(5))
25 #define LIS3MDL_MAG_DO_MASK (BIT(4) | BIT(3) | BIT(2))
27 #define LIS3MDL_FAST_ODR_MASK BIT(1)
29 #define LIS3MDL_ST_MASK BIT(0)
38 #define LIS3MDL_FS_MASK (BIT(6) | BIT(5))
40 #define LIS3MDL_REBOOT_MASK BIT(3)
42 #define LIS3MDL_SOFT_RST_MASK BIT(2)
45 #define LIS3MDL_FS_IDX ((CONFIG_LIS3MDL_FS / 4) - 1)
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/Zephyr-latest/drivers/display/
DKconfig.microbit4 # SPDX-License-Identifier: Apache-2.0
7 bool "BBC micro:bit 5x5 LED Display support"
12 LED matrix display on the BBC micro:bit.
17 default 40
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx-espi-vws-ex-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
9 #include <nuvoton/npcx/npcx-espi-vws-map.dtsi>
13 * |--------------------------------------------------------------------------|
14 * | VW idx | SLV reg | Wire Bit 3 | Wire Bit 2 | Wire Bit 1| Wire Bit 0 |
15 * |--------------------------------------------------------------------------|
16 * | Input (Master-to-Slave) Virtual Wires |
17 * |--------------------------------------------------------------------------|
19 * |--------------------------------------------------------------------------|
20 * | Output (Slave-to-Master) Virtual Wires |
21 * |--------------------------------------------------------------------------|
[all …]
/Zephyr-latest/drivers/dma/
Ddma_iproc_pax_v1.h4 * SPDX-License-Identifier: Apache-2.0
19 #define RM_COMM_CONTROL_CONFIG_DONE BIT(2)
21 #define RM_COMM_CONTROL_LINE_INTR_EN BIT(4)
23 #define RM_COMM_CONTROL_AE_TIMEOUT_EN BIT(5)
43 /* Bits 0:1 ignored by PAX DMA, i.e. 4-byte address alignment */
51 * Per-ring memory, with 8K & 4K alignment
65 uint64_t bdcount : 5; /*bdcount 40:36*/
66 uint64_t prot : 2; /*prot 41:40*/
107 uint64_t toggle : 1; /*Toggle Bit:58*/
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
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Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
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Dti,ina219.yaml2 # SPDX-License-Identifier: Apache-2.0
8 include: [sensor-device.yaml, i2c-device.yaml]
11 lsb-microamp:
17 example: 100 -> ~3A
18 shunt-milliohm:
31 The default of 32V is the power-on reset value of the device.
35 - 0
36 - 1
42 0 = 1 -> ±40 mV
43 1 = /2 -> ±80 mV
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Dvishay,vcnl36825t.yaml2 # SPDX-License-Identifier: Apache-2.0
10 include: [sensor-device.yaml, i2c-device.yaml]
13 operation-mode:
19 - "auto": the sensor performs sampling continuously,
20 - "force": the sampling is performed on every fetch command.
24 Note: "force"-mode only available if low-power mode inactive.
26 measurement-period:
28 default: 40
29 enum: [10, 20, 40, 80, 160, 320]
34 - [10, 80] ms only if low power mode is inactive
[all …]
/Zephyr-latest/arch/posix/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
14 default 44 if 64BIT && STACK_SENTINEL
15 default 40 if 64BIT
/Zephyr-latest/subsys/logging/
DKconfig.misc2 # SPDX-License-Identifier: Apache-2.0
29 depends on !64BIT && !CBPRINTF_PACKAGE_HEADER_STORE_CREATION_FLAGS
32 Dedicated code for handling simple log messages (0-2 32 bit word arguments).
33 Approximately, 70%-80% log messages in the application fit into that category.
34 Depending on the architecture code size reduction is from 0-40% (highest seen on
35 RISCV32) and execution time also up to 40%.
109 read-only string arguments in the package. This should be selected by
/Zephyr-latest/soc/xlnx/zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
19 #define MIO_PIN_DISABLE_RCVR_MASK BIT(13)
22 #define MIO_PIN_PULLUP_MASK BIT(12)
28 #define MIO_PIN_SPEED_MASK BIT(8)
37 #define MIO_PIN_L1_SEL_MASK BIT(2)
40 #define MIO_PIN_L0_SEL_MASK BIT(1)
43 #define MIO_PIN_TRI_ENABLE_MASK BIT(0)
148 #define MIO40 40
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
180 #define MIO_GROUP_SPI0_2_GRP_PINS 40, 41, 45
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/Zephyr-latest/arch/posix/include/
Dposix_core.h4 * SPDX-License-Identifier: Apache-2.0
34 * Currently there are 4 pointers + 2 ints, on a 32-bit native posix
36 * For a 64-bit implementation the recommended stack size will be
37 * 40 bytes ( 4*8 + 2*4 ).
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.intel_vtd1 # Intel VT-D interrupt remapping controller configuration
4 # SPDX-License-Identifier: Apache-2.0
7 bool "Intel VT-D interrupt remapping controller"
10 depends on !BOARD_QEMU_X86_64 && ACPI && X86 && 64BIT && PCIE_MSI_MULTI_VECTOR
13 Such interrupt remapping hardware is provided through Intel VT-D
14 technology. It's being used, currently, only for MSI/MSI-X
15 multi-vector support. If you have such PCIe device requiring
16 multi-vector support, you will need to enable this.
21 bool "XAPIC mode pass-through"
33 default 40
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/Zephyr-latest/drivers/ieee802154/
Dieee802154_cc1200_regs.h1 /* ieee802154_cc1200_regs.h - Registers definition for TI CC1200 */
6 * SPDX-License-Identifier: Apache-2.0
14 #define CC1200_ACCESS_RD BIT(7)
16 #define CC1200_ACCESS_BURST BIT(6)
21 #define GPIO3_ATRAN BIT(7)
22 #define GPIO3_INV BIT(6)
26 #define GPIO2_ATRAN BIT(7)
27 #define GPIO2_INV BIT(6)
31 #define GPIO1_ATRAN BIT(7)
32 #define GPIO1_INV BIT(6)
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Dieee802154_dw1000_regs.h4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
73 /* Frame Filtering Enable. This bit enables the frame filtering functionality */
75 /* Frame Filtering Behave as a Co-ordinator */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
123 /* Automatic Acknowledgement Pending bit control */
126 /* System Time Counter (40-bit) */
[all …]
/Zephyr-latest/include/zephyr/arch/arm/cortex_a_r/
Dcpu.h3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 * SPDX-License-Identifier: Apache-2.0
16 * SCTLR register bit assignments
52 /* Armv8-R AArch32 architecture profile */
54 #define SCTLR_M_BIT BIT(0)
55 #define SCTLR_A_BIT BIT(1)
56 #define SCTLR_C_BIT BIT(2)
57 #define SCTLR_I_BIT BIT(12)
59 /* Armv8-R Cortex-R52 Cache Segregation Control Register */
66 #define HSCTLR_RES1 (BIT(29) | BIT(28) | BIT(23) | \
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/Zephyr-latest/tests/drivers/can/api/src/
Dcommon.c5 * SPDX-License-Identifier: Apache-2.0
26 * @brief Standard (11-bit) CAN ID frame 1.
36 * @brief Standard (11-bit) CAN ID frame 2.
46 * @brief Extended (29-bit) CAN ID frame 1.
56 * @brief Extended (29-bit) CAN ID frame 1.
66 * @brief Standard (11-bit) CAN ID RTR frame 1.
76 * @brief Extended (29-bit) CAN ID RTR frame 1.
87 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
95 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45,
101 * @brief Standard (11-bit) CAN ID frame 1 with CAN FD payload.
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Dsmartbond-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
51 #define SMARTBOND_FUNC_PORT3_DCF 40
67 /** Definitions of bit positions and bit masks in pinmux */

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