Lines Matching +full:40 +full:- +full:bit

4  * SPDX-License-Identifier: Apache-2.0
19 #define MIO_PIN_DISABLE_RCVR_MASK BIT(13)
22 #define MIO_PIN_PULLUP_MASK       BIT(12)
28 #define MIO_PIN_SPEED_MASK        BIT(8)
37 #define MIO_PIN_L1_SEL_MASK       BIT(2)
40 #define MIO_PIN_L0_SEL_MASK       BIT(1)
43 #define MIO_PIN_TRI_ENABLE_MASK   BIT(0)
148 #define MIO40 40
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
180 #define MIO_GROUP_SPI0_2_GRP_PINS          40, 41, 45
202 #define MIO_GROUP_SDIO0_2_GRP_PINS         40, 41, 42, 43, 44, 45
237 #define MIO_GROUP_CAN1_8_GRP_PINS          40, 41
260 #define MIO_GROUP_UART1_8_GRP_PINS         40, 41
282 #define MIO_GROUP_I2C1_7_GRP_PINS          40, 41
291 #define MIO_GROUP_TTC1_2_GRP_PINS          40, 41
337 #define MIO_GROUP_GPIO0_40_GRP_PINS        40
352 #define MIO_GROUP_USB1_0_GRP_PINS          40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51
360 /* Iterate over each pinctrl-n phandle child */
367  *   - Iterate over each pin in group and populate pinctrl_soc_pin_t
369  *   - Iterate over each pin in pins and populate pinctrl_soc_pin_t