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/Zephyr-latest/arch/sparc/core/
Dtrap_table_svt.S4 * SPDX-License-Identifier: Apache-2.0
9 * single-vector trap model, defined in SPARC V8E. The processor
11 * there, two levels of look-up tables are used to find the trap
14 * - Execution time is constant.
15 * - Condition flags are not modified.
16 * - Provides handler with PSR in l0, TBR in l6
17 * - This SVT implementation is less than 400 bytes long. (An MVT
50 srl %l6, 4, %l3
59 .align 4
61 .word __sparc_trap_table_svt_00
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/Zephyr-latest/arch/arm/core/cortex_m/
Dirq_relay.S4 * SPDX-License-Identifier: Apache-2.0
10 * @brief IRQ relay vector table and relay handler for Cortex-M0 or
11 * Armv8-M baseline SoCs
13 * In certain ARMv6-M and Armv8-M baseline cores the vector table address can
42 * The size of IRQ vector is 4 bytes, the offset within vector table
43 * is the IRQ number times 4 (aka r0 << 2). As know as the r1 stored
53 .word z_main_stack + CONFIG_MAIN_STACK_SIZE
55 .word z_arm_reset
57 .word __vector_relay_handler /* nmi */
58 .word __vector_relay_handler /* hard fault */
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/Zephyr-latest/dts/bindings/dma/
Dgd,gd32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
12 - bit 6-7: Direction (see dma.h)
13 - 0x0: MEMORY to MEMORY
14 - 0x1: MEMORY to PERIPH
15 - 0x2: PERIPH to MEMORY
16 - 0x3: reserved for PERIPH to PERIPH
18 - bit 9: Peripheral address increase
19 - 0x0: no address increment between transfers
20 - 0x1: increment address between transfers
22 - bit 10: Memory address increase
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Dandestech,atcdmac300.yaml4 # SPDX-License-Identifier: Apache-2.0
8 include: dma-controller.yaml
17 chain-transfer:
20 "#dma-cells":
23 dma-cells:
24 - channel
25 - slot
26 - channel-config
33 3. channel-config: A 32bit mask specifying the DMA channel configuration
35 -bit 0-1 : Direction (see dma.h)
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Dst,stm32-dma-v1.yaml2 # SPDX-License-Identifier: Apache-2.0
10 described in the dma.txt file, using a four-cell specifier for each
12 1. channel: the dma stream from 0 to <dma-requests>
14 this value is 0 for Memory-to-memory transfers
15 or a value between <1> .. <dma-generators> (not supported yet)
16 or a value between <dma-generators>+1 .. <dma-generators>+<dma-requests>
17 3. channel-config: A 32bit mask specifying the DMA channel configuration
19 -bit 6-7 : Direction (see dma.h)
24 -bit 9 : Peripheral Increment Address
27 -bit 10 : Memory Increment Address
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Dst,stm32-dmamux.yaml2 # SPDX-License-Identifier: Apache-2.0
9 DMAMUX clients connected to the STM32 DMA ultiplexer must use a two-cell specifier
11 1. channel: the mux channel from 0 to <dma-channels> - 1
13 3. channel-config: A 32bit mask specifying the DMA channel configuration
15 -bit 6-7 : Direction (see dma.h)
20 -bit 9 : Peripheral Increment Address
23 -bit 10 : Memory Increment Address
26 -bit 11-12 : Peripheral data size
28 0x1: Half-word (16 bits)
29 0x2: Word (32 bits)
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Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
30 0x1: Half-word (16 bits)
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/Zephyr-latest/drivers/ethernet/
Deth_stellaris.c5 * SPDX-License-Identifier: Apache-2.0
36 value |= mac_addr[4]; in eth_stellaris_assign_mac()
43 struct eth_stellaris_runtime *dev_data = dev->data; in eth_stellaris_flush()
45 if (dev_data->tx_pos != 0) { in eth_stellaris_flush()
46 sys_write32(dev_data->tx_word, REG_MACDATA); in eth_stellaris_flush()
47 dev_data->tx_pos = 0; in eth_stellaris_flush()
48 dev_data->tx_word = 0U; in eth_stellaris_flush()
54 struct eth_stellaris_runtime *dev_data = dev->data; in eth_stellaris_send_byte()
56 dev_data->tx_word |= byte << (dev_data->tx_pos * 8); in eth_stellaris_send_byte()
57 dev_data->tx_pos++; in eth_stellaris_send_byte()
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/Zephyr-latest/drivers/led_strip/
Dws2812_i2s.c5 * https://electronut.in/nrf52-i2s-ws2812/
7 * Note: the word "word" refers to a 32-bit integer unless otherwise stated.
10 * This refers to the "I2S word or channel select" clock.
11 * The I2S peripheral sends two 16-bit channel values for each clock period.
12 * A single LED color (8 data bits) will take up one 32-bit word or one LRCK
15 * SPDX-License-Identifier: Apache-2.0
28 #include <zephyr/dt-bindings/led/led.h>
49 /* Serialize an 8-bit color channel value into two 16-bit I2S values (or 1 32-bit
50 * word).
54 uint32_t word = 0; in ws2812_i2s_ser() local
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/Zephyr-latest/include/zephyr/arch/x86/ia32/
Dthread.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Per-arch thread definition
27 * cases a 4 byte boundary is sufficient.
33 #define FP_REG_SET_ALIGN 4
55 * The following structure defines the set of 'non-volatile' integer registers.
65 * The following registers are considered non-volatile, i.e.
66 * callee-save,
94 unsigned char reg[10]; /* 80 bits: ST[0-7] */
101 * "Intel(r) 64 and IA-32 Architectures Software Developer's Manual
103 * Memory, 32-Bit Format.
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/Zephyr-latest/drivers/entropy/
Dentropy_smartbond.c4 * SPDX-License-Identifier: Apache-2.0
37 (CONFIG_ENTROPY_SMARTBOND_ISR_POOL_SIZE - 1)) == 0,
41 (CONFIG_ENTROPY_SMARTBOND_THR_POOL_SIZE - 1)) == 0,
86 CRG_TOP->CLK_AMBA_REG |= CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk; in trng_enable()
87 TRNG->TRNG_CTRL_REG = TRNG_TRNG_CTRL_REG_TRNG_ENABLE_Msk; in trng_enable()
95 CRG_TOP->CLK_AMBA_REG &= ~CRG_TOP_CLK_AMBA_REG_TRNG_CLK_ENABLE_Msk; in trng_enable()
96 TRNG->TRNG_CTRL_REG = 0; in trng_enable()
106 return TRNG->TRNG_FIFOLVL_REG & FIFO_COUNT_MASK; in trng_available()
114 static int random_word_get(uint8_t buf[4]) in random_word_get() argument
116 uint32_t word = 0; in random_word_get() local
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/Zephyr-latest/drivers/dai/nxp/sai/
DKconfig.sai2 # SPDX-License-Identifier: Apache-2.0
25 int "Size (in bytes) of a FIFO word"
26 default 4
29 FIFO word.
/Zephyr-latest/tests/drivers/fuel_gauge/sbs_gauge/src/
Dtest_sbs_gauge.c5 * SPDX-License-Identifier: Apache-2.0
47 int ret = fuel_gauge_get_props(fixture->dev, prop_types, props, ARRAY_SIZE(props)); in ZTEST_USER_F()
49 zassert_equal(ret, -ENOTSUP, "Getting bad property has a good status."); in ZTEST_USER_F()
60 int ret = fuel_gauge_set_props(fixture->dev, prop_types, props, ARRAY_SIZE(props)); in ZTEST_USER_F()
62 zassert_equal(ret, -ENOTSUP); in ZTEST_USER_F()
74 /* Set Manufacturer's Access to arbitrary word */ in ZTEST_USER_F()
84 /* Set Manufacturer's Access to arbitrary word */ in ZTEST_USER_F()
88 int ret = fuel_gauge_set_props(fixture->dev, prop_types, props, ARRAY_SIZE(props)); in ZTEST_USER_F()
90 zassert_equal(ret, -ENOTSUP); in ZTEST_USER_F()
95 uint16_t word = BIT(15) | BIT(0); in ZTEST_USER_F() local
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/Zephyr-latest/arch/arm/core/
Dvector_table.ld2 * Copyright (c) 2019 - 2020 Nordic Semiconductor ASA
4 * SPDX-License-Identifier: Apache-2.0
17 * of the vector table is 64-word aligned.
19 . = ALIGN( 1 << LOG2CEIL(4 * 64) );
22 * of the vector table is 32-word aligned.
24 . = ALIGN( 1 << LOG2CEIL(4 * 32) );
34 * setting in any Cortex-M implementation (might not be required in every
35 * Cortex-M processor).
37 . = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
42 * For AArch32 (A/R), VBAR has Bits [4:0] = RES0.
/Zephyr-latest/soc/nxp/rw/
Dfirmwares.ld4 * SPDX-License-Identifier: Apache-2.0
11 * issue, so add a padding of one word */
13 . = ALIGN(4);
15 . += 4;
19 . = ALIGN(4);
/Zephyr-latest/samples/net/sockets/sntp_client/src/
Dmain.c5 * SPDX-License-Identifier: Apache-2.0
45 rv = sntp_query(&ctx, 4 * MSEC_PER_SEC, &sntp_time); in main()
52 LOG_INF("time since Epoch: high word: %u, low word: %u", in main()
80 LOG_INF("time since Epoch: high word: %u, low word: %u", in main()
/Zephyr-latest/include/zephyr/arch/arc/asm-compat/
Dassembler.h1 /* SPDX-License-Identifier: Apache-2.0 */
7 * Top level include file providing ISA pseudo-mnemonics for use in assembler
10 * - Helps code reuse across ARC64/ARC32/ARCv2
11 * e.g. "LDR" maps to 'LD' on 32-bit ISA, 'LDL' on 64-bit ARCv2/ARC64
13 * - Provides emulation with multiple instructions if the case be
16 * - Looks more complex than it really is: mainly because Kconfig defines
34 #include "asm-macro-64-bit-mwdt.h"
36 #include "asm-macro-64-bit-gnu.h"
40 #define ARC_PTR .word
41 #define ARC_REGSZ 4
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/Zephyr-latest/include/zephyr/drivers/
Dsmbus.h4 * SPDX-License-Identifier: Apache-2.0
49 * 0 1 2 3 4 5 6 7 8 9 0
50 * +-+-+-+-+-+-+-+-+-+-+-+
52 * +-+-+-+-+-+-+-+-+-+-+-+
64 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
65 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
72 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
73 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
75 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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/Zephyr-latest/dts/bindings/dai/
Dnxp,dai-esai.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dai-esai"
13 dai-index:
21 tx-fifo-watermark:
29 rx-fifo-watermark:
37 fifo-depth:
48 that the sanity check for tx/rx-fifo-watermark uses DEFAULT_FIFO_DETPH
52 word-width:
55 This property is used to specify the width of a word. If unspecified,
56 the word width used will be 24.
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/Zephyr-latest/doc/kernel/services/smp/
Dsmpinit.svg1 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
2 <!-- Created with Inkscape (http://www.inkscape.org/) -->
7 xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#"
10 xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd"
30 transform="matrix(-0.4,0,0,-0.4,-4,0)"
31 …style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stro…
32 d="M 0,0 5,-5 -12.5,0 5,5 Z"
34 inkscape:connector-curvature="0" />
45 transform="matrix(0.4,0,0,0.4,4,0)"
46 …style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stro…
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/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_espi_vw.h4 * SPDX-License-Identifier: Apache-2.0
13 /* Master to Slave VW register: 96-bit (3 32 bit registers) */
14 /* 32-bit word 0 (bits[31:0]) */
28 /* 32-bit word 1 (bits[63:32]) */
29 #define ESPI_M2SW1_OFS 4u
39 /* 0 <= n < 4 */
43 /* 32-bit word 2 (bits[95:64]) */
54 /* 0 <= n < 4 */
71 #define ESPI_IRQ_SEL_DIS 4
77 /* Slave to Master VW register: 64-bit (2 32 bit registers) */
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/Zephyr-latest/tests/lib/mpsc_pbuf/src/
Dconcurrent.c4 * SPDX-License-Identifier: Apache-2.0
27 static uint32_t track_mask[4][12];
28 static uint32_t track_base_idx[4];
32 uint32_t idx[4];
45 #define DATA_BITS (32 - MPSC_PBUF_HDR_BITS - LEN_BITS - CTX_BITS)
60 uint32_t ridx = idx - track_base_idx[ctx]; in track_produce()
61 uint32_t word = ridx / MASK_BITS; in track_produce() local
62 uint32_t bit = ridx & (MASK_BITS - 1); in track_produce()
65 track_mask[ctx][word] |= BIT(bit); in track_produce()
73 uint32_t ridx = idx - base_idx; in track_consume()
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/Zephyr-latest/samples/subsys/llext/shell_loader/
DREADME.rst1 .. zephyr:code-sample:: llext-shell-loader
3 :relevant-api: llext_apis
21 .. zephyr-app-commands::
22 :zephyr-app: samples/subsys/llext/shell_loader
33 All the llext system related commands are available as sub-commands of llext
36 .. code-block:: console
39 llext - Loadable extension commands
61 .. code-block:: console
63 …$ arm-zephyr-eabi-gcc -mlong-calls -mthumb -c -o hello_world.elf tests/subsys/llext/hello_world/he…
64 $ arm-zephyr-eabi-objdump -r -d -x hello_world.elf
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/Zephyr-latest/arch/arm/core/mmu/
Darm_mmu_priv.h7 * SPDX-License-Identifier: Apache-2.0
15 * ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition
18 * Chapter B3.5.1, fig. B3-4 and B3-5, p. B3-1323 f.
70 /* <-- end MP-/non-MP-specific */
84 #define ARM_MMU_L2_PT_INDEX(pt) ((uint32_t)pt - (uint32_t)l2_page_tables) /\
93 uint32_t domain : 4;
109 uint32_t domain : 4;
117 uint32_t word; member
153 uint32_t word; member
186 * data derived from a memory region's attr flags word in the format
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/Zephyr-latest/samples/boards/nxp/mimxrt595_evk/system_off/
DREADME.rst1 .. zephyr:code-sample:: mimxrt595_evk_system_off
3 :relevant-api: sys_poweroff
5 Use soft-off on MIMXRT595-EVK.
13 * Busy-wait for 2 seconds
20 This application uses MIMXRT595-EVK for the demo.
25 .. zephyr-app-commands::
26 :zephyr-app: samples/boards/nxp/mimxrt595_evk/system_off
36 4. Device will turn itself off using deep power down mode. RTC alarm
41 MIMXRT595-EVK core output
42 --------------------------
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