Lines Matching +full:4 +full:- +full:word
4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Per-arch thread definition
27 * cases a 4 byte boundary is sufficient.
33 #define FP_REG_SET_ALIGN 4
55 * The following structure defines the set of 'non-volatile' integer registers.
65 * The following registers are considered non-volatile, i.e.
66 * callee-save,
94 unsigned char reg[10]; /* 80 bits: ST[0-7] */
101 * "Intel(r) 64 and IA-32 Architectures Software Developer's Manual
103 * Memory, 32-Bit Format.
107 unsigned short fcw; /* 2 : x87 FPU control word */
109 unsigned short fsw; /* 2 : x87 FPU status word */
111 unsigned short ftw; /* 2 : x87 FPU tag word */
113 unsigned int fpuip; /* 4 : x87 FPU instruction pointer offset */
117 unsigned int fpudp; /* 4 : x87 FPU instr operand ptr offset */
120 tFpReg fpReg[8]; /* 80 : ST0 -> ST7 */
128 unsigned char reg[10]; /* 80 bits: ST[0-7] or MM[0-7] */
135 unsigned char reg[16]; /* 128 bits: XMM[0-7] */
142 * "Intel 64 and IA-32 Architectures Software Developer's Manual
143 * Volume 2A: Instruction Set Reference, A-M", except for the bytes from offset
153 unsigned short fcw; /* 2 : x87 FPU control word */
154 unsigned short fsw; /* 2 : x87 FPU status word */
155 unsigned char ftw; /* 1 : x87 FPU abridged tag word */
158 unsigned int fpuip; /* 4 : x87 FPU instruction pointer offset */
161 unsigned int fpudp; /* 4 : x87 FPU instr operand ptr offset */
164 unsigned int mxcsr; /* 4 : MXCSR register state */
165 unsigned int mxcsrMask; /* 4 : MXCSR register mask */
224 * Un-set for supervisor threads.