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/Zephyr-latest/samples/shields/x_nucleo_53l0a1/src/
Ddisplay_7seg.h7 * SPDX-License-Identifier: Apache-2.0
15 * ---
17 * -2-
19 * ---
20 * 4
25 #define CHAR_0 (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
26 #define CHAR_1 (BIT(5) | BIT(6))
27 #define CHAR_2 (BIT(0) | BIT(2) | BIT(3) | BIT(4) | BIT(5))
28 #define CHAR_3 (BIT(2) | BIT(3) | BIT(4) | BIT(5) | BIT(6))
29 #define CHAR_4 (BIT(1) | BIT(2) | BIT(5) | BIT(6))
[all …]
/Zephyr-latest/drivers/audio/
Dtas6422dac.h4 * SPDX-License-Identifier: Apache-2.0
18 #define MODE_CTRL_RESET BIT(7)
19 #define MODE_CTRL_RESET_MASK BIT(7)
20 #define MODE_CTRL_PBTL_CH12 BIT(4)
21 #define MODE_CTRL_PBTL_CH12_MASK BIT(4)
22 #define MODE_CTRL_CH1_LO_MODE BIT(3)
23 #define MODE_CTRL_CH1_LO_MODE_MASK BIT(3)
24 #define MODE_CTRL_CH2_LO_MODE BIT(2)
25 #define MODE_CTRL_CH2_LO_MODE_MASK BIT(2)
29 #define MISC_CTRL_1_HPF_BYPASS BIT(7)
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/Zephyr-latest/drivers/sensor/st/lsm9ds0_gyro/
Dlsm9ds0_gyro.h1 /* sensor_lsm9ds0_gyro.h - header file for LSM9DS0 gyroscope sensor driver */
6 * SPDX-License-Identifier: Apache-2.0
23 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_DR (BIT(7) | BIT(6))
25 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_BW (BIT(5) | BIT(4))
26 #define LSM9DS0_GYRO_SHIFT_CTRL_REG1_G_BW 4
27 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_PD BIT(3)
29 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_ZEN BIT(2)
31 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_XEN BIT(1)
33 #define LSM9DS0_GYRO_MASK_CTRL_REG1_G_YEN BIT(0)
37 #define LSM9DS0_GYRO_MASK_CTRL_REG2_G_HPM (BIT(5) | BIT(4))
[all …]
/Zephyr-latest/drivers/sensor/st/lsm6dsl/
Dlsm6dsl.h1 /* sensor_lsm6dsl.h - header file for LSM6DSL accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
29 #define LSM6DSL_MASK_FUNC_CFG_EN BIT(7)
31 #define LSM6DSL_MASK_FUNC_CFG_EN_B BIT(5)
35 #define LSM6DSL_MASK_SENSOR_SYNC_TIME_FRAME_TPH (BIT(3) | BIT(2) | \
36 BIT(1) | BIT(0))
40 #define LSM6DSL_MASK_SENSOR_SYNC_RES_RATIO (BIT(1) | BIT(0))
44 #define LSM6DSL_MASK_FIFO_CTRL1_FTH (BIT(7) | BIT(6) | \
45 BIT(5) | BIT(4) | \
46 BIT(3) | BIT(2) | \
[all …]
/Zephyr-latest/drivers/sensor/st/lsm9ds0_mfd/
Dlsm9ds0_mfd.h1 /* sensor_lsm9ds0_mfd.h - header file for LSM9DS0 accelerometer, magnetometer
8 * SPDX-License-Identifier: Apache-2.0
22 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMOR BIT(7)
24 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMOR BIT(6)
26 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMOR BIT(5)
28 #define LSM9DS0_MFD_MASK_STATUS_REG_M_XMOR BIT(4)
29 #define LSM9DS0_MFD_SHIFT_STATUS_REG_M_XMOR 4
30 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZYXMDA BIT(3)
32 #define LSM9DS0_MFD_MASK_STATUS_REG_M_ZMDA BIT(2)
34 #define LSM9DS0_MFD_MASK_STATUS_REG_M_YMDA BIT(1)
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/Zephyr-latest/drivers/sensor/st/lps22hb/
Dlps22hb.h1 /* sensor_lps25hb.h - header file for LPS22HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
22 #define LPS22HB_MASK_INTERRUPT_CFG_AUTORIFP BIT(7)
24 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_ARP BIT(6)
26 #define LPS22HB_MASK_INTERRUPT_CFG_AUTOZERO BIT(5)
28 #define LPS22HB_MASK_INTERRUPT_CFG_RESET_AZ BIT(4)
29 #define LPS22HB_SHIFT_INTERRUPT_CFG_RESET_AZ 4
30 #define LPS22HB_MASK_INTERRUPT_CFG_DIFF_EN BIT(3)
32 #define LPS22HB_MASK_INTERRUPT_CFG_LIR BIT(2)
34 #define LPS22HB_MASK_INTERRUPT_CFG_PL_E BIT(1)
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/Zephyr-latest/drivers/sensor/apds9253/
Dapds9253.h5 * SPDX-License-Identifier: Apache-2.0
15 #define APDS9253_MAIN_CTRL_SAI_LS BIT(5)
16 #define APDS9253_MAIN_CTRL_SW_RESET BIT(4)
17 #define APDS9253_MAIN_CTRL_RGB_MODE BIT(2)
18 #define APDS9253_MAIN_CTRL_LS_EN BIT(1)
21 #define APDS9253_LS_MEAS_RATE_RES_MASK GENMASK(6, 4)
23 #define APDS9253_LS_MEAS_RATE_RES_19BIT_200MS BIT(4)
24 #define APDS9253_LS_MEAS_RATE_RES_18BIT_100MS BIT(5) /* default */
25 #define APDS9253_LS_MEAS_RATE_RES_17BIT_50MS (BIT(5) | BIT(4))
26 #define APDS9253_LS_MEAS_RATE_RES_16BIT_25MS BIT(6)
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/Zephyr-latest/drivers/sensor/st/lsm6ds0/
Dlsm6ds0.h1 /* sensor_lsm6ds0.h - header file for LSM6DS0 accelerometer, gyroscope and
8 * SPDX-License-Identifier: Apache-2.0
19 #define LSM6DS0_MASK_ACT_THS_SLEEP_ON_INACT_EN BIT(7)
21 #define LSM6DS0_MASK_ACT_THS_ACT_THS (BIT(6) | BIT(5) | BIT(4) | \
22 BIT(3) | BIT(2) | BIT(1) | \
23 BIT(0))
29 #define LSM6DS0_MASK_INT_GEN_CFG_XL_AOI_XL BIT(7)
31 #define LSM6DSO_MASK_INT_GEN_CFG_XL_6D BIT(6)
33 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZHIE_XL BIT(5)
35 #define LSM6DS0_MASK_INT_GEN_CFG_XL_ZLIE_XL BIT(4)
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/Zephyr-latest/drivers/gpio/
Dgpio_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
35 /* gpio port data register (bit mapping to pin) */
39 /* gpio port data mirror register (bit mapping to pin) */
41 /* gpio port output type register (bit mapping to pin) */
57 ((struct gpio_ite_data *)(dev)->data)
60 ((const struct gpio_ite_cfg *)(dev)->config)
63 * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on in wuesr()
[all …]
/Zephyr-latest/drivers/sensor/st/lps25hb/
Dlps25hb.h1 /* sensor_lps25hb.h - header file for LPS25HB pressure and temperature
8 * SPDX-License-Identifier: Apache-2.0
26 #define LPS25HB_MASK_RES_CONF_AVGT (BIT(3) | BIT(2))
28 #define LPS25HB_MASK_RES_CONF_AVGP (BIT(1) | BIT(0))
32 #define LPS25HB_MASK_CTRL_REG1_PD BIT(7)
34 #define LPS25HB_MASK_CTRL_REG1_ODR (BIT(6) | BIT(5) | BIT(4))
35 #define LPS25HB_SHIFT_CTRL_REG1_ODR 4
36 #define LPS25HB_MASK_CTRL_REG1_DIFF_EN BIT(3)
38 #define LPS25HB_MASK_CTRL_REG1_BDU BIT(2)
40 #define LPS25HB_MASK_CTRL_REG1_RESET_AZ BIT(1)
[all …]
/Zephyr-latest/drivers/sensor/apds9960/
Dapds9960.h5 * SPDX-License-Identifier: Apache-2.0
14 #define APDS9960_ENABLE_GEN BIT(6)
15 #define APDS9960_ENABLE_PIEN BIT(5)
16 #define APDS9960_ENABLE_AIEN BIT(4)
17 #define APDS9960_ENABLE_WEN BIT(3)
18 #define APDS9960_ENABLE_PEN BIT(2)
19 #define APDS9960_ENABLE_AEN BIT(1)
20 #define APDS9960_ENABLE_PON BIT(0)
32 #define APDS9960_PERS_PPERS (BIT(4) | BIT(5) | BIT(6) | BIT(7))
33 #define APDS9960_APERS_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3))
[all …]
/Zephyr-latest/drivers/charger/
Dbq24190.h4 * SPDX-License-Identifier: Apache-2.0
12 #define BQ24190_REG_ISC_EN_HIZ_MASK BIT(7)
18 /* Power-On Configuration */
20 #define BQ24190_REG_POC_RESET_MASK BIT(7)
23 #define BQ24190_REG_POC_WDT_RESET_MASK BIT(6)
25 #define BQ24190_REG_POC_CHG_CONFIG_MASK GENMASK(5, 4)
26 #define BQ24190_REG_POC_CHG_CONFIG_SHIFT 4
35 #define BQ24190_REG_POC_BOOST_LIM_MASK BIT(0)
46 #define BQ24190_REG_CCC_FORCE_20PCT_MASK BIT(0)
49 /* Pre-charge/Termination Current Cntl */
[all …]
/Zephyr-latest/drivers/ieee802154/
Dieee802154_mcr20a_regs.h1 /* ieee802154_mcr20a_regs.h - Registers definition for NXP MCR20A */
6 * SPDX-License-Identifier: Apache-2.0
11 * which are used in the macros for the bit field manipulation.
47 #define MCR20A_REG_READ (BIT(7))
48 #define MCR20A_BUF_READ (BIT(7) | BIT(6))
49 #define MCR20A_BUF_BYTE_READ (BIT(7) | BIT(6) | BIT(5))
51 #define MCR20A_BUF_WRITE (BIT(6))
52 #define MCR20A_BUF_BYTE_WRITE (BIT(6) | BIT(5))
93 /* ---------------- (0x27) */
112 /* ---------------- (0x3a) */
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
22 #define MCP251XFD_RAM_ALIGNMENT 4
32 #define MCP251XFD_RX_FIFO_ITEM_SIZE (4 + 8 + MCP251XFD_PAYLOAD_SIZE)
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
53 #define MCP251XFD_REG_SIZE 4
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
95 #define MCP251XFD_REG_CON_MODE_CONFIG 4
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
[all …]
Dcan_sja1000_priv.h4 * SPDX-License-Identifier: Apache-2.0
17 #define CAN_SJA1000_IER (4U)
51 #define CAN_SJA1000_MOD_RM BIT(0)
52 #define CAN_SJA1000_MOD_LOM BIT(1)
53 #define CAN_SJA1000_MOD_STM BIT(2)
54 #define CAN_SJA1000_MOD_AFM BIT(3)
55 #define CAN_SJA1000_MOD_SM BIT(4)
58 #define CAN_SJA1000_CMR_TR BIT(0)
59 #define CAN_SJA1000_CMR_AT BIT(1)
60 #define CAN_SJA1000_CMR_RRB BIT(2)
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/Zephyr-latest/drivers/ipm/
Dipm_nrfx_ipc.h4 * SPDX-License-Identifier: Apache-2.0
13 * Message channels are one-way connections between cores.
19 * SIGNAL0 -> CHANNEL0 -> EVENT0
24 * EVENT1 <- CHANNEL1 <- SIGNAL1
36 IPC_EVENT_BIT(4) | \
52 [0] = BIT(0),
53 [1] = BIT(1),
54 [2] = BIT(2),
55 [3] = BIT(3),
56 [4] = BIT(4),
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_timers.h4 * SPDX-License-Identifier: Apache-2.0
25 * 32-bit R/W
26 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
32 * 32-bit R/W
33 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
69 #define MCHP_BTMR_CTRL_SRESET_POS 4u
74 /** @brief Basic Timer(32 and 16 bit) registers. Total size = 20(0x14) bytes */
87 * Set count resolution in bit[0]
93 #define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS)
95 #define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS)
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/Zephyr-latest/drivers/sensor/ams/tsl2540/
Dtsl2540.h2 * Copyright (c) 2022 T-Mobile USA, Inc.
4 * SPDX-License-Identifier: Apache-2.0
36 #define TSL2540_AGAIN_S4 4
55 /* ENABLE(0x80: 0x00): Reserved:7:4 | WEN:3 | Reserved:2 | AEN:1 | PON:0 */
57 #define TSL2540_ENABLE_MASK (BIT(3) | BIT(1) | BIT(0))
58 #define TSL2540_ENABLE_CONF (BIT(3) | BIT(1) | BIT(0))
59 #define TSL2540_ENABLE_AEN_PON (BIT(1) | BIT(0))
62 /* CRG3(0xAB: 0x0C): INT_READ_CLEAR:7 | Reserved:6:5 | SAI:4 | Reserved:3:0 */
64 #define TSL2540_CFG3_MASK (BIT(7) | BIT(4))
65 #define TSL2540_CFG3_CONF (BIT(7) | BIT(4))
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
33 #define SSCR0_FRF DAI_INTEL_SSP_MASK(5, 4)
34 #define SSCR0_MOT DAI_INTEL_SSP_SET_BITS(5, 4, 0)
35 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
36 #define SSCR0_NAT DAI_INTEL_SSP_SET_BITS(5, 4, 2)
37 #define SSCR0_PSP DAI_INTEL_SSP_SET_BITS(5, 4, 3)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
32 #define SSCR0_FRF DAI_INTEL_SSP_MASK(5, 4)
33 #define SSCR0_MOT DAI_INTEL_SSP_SET_BITS(5, 4, 0)
34 #define SSCR0_TI DAI_INTEL_SSP_SET_BITS(5, 4, 1)
35 #define SSCR0_NAT DAI_INTEL_SSP_SET_BITS(5, 4, 2)
36 #define SSCR0_PSP DAI_INTEL_SSP_SET_BITS(5, 4, 3)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
[all …]
/Zephyr-latest/drivers/sensor/st/lis2dh/
Dlis2dh.h4 * SPDX-License-Identifier: Apache-2.0
29 #define LIS2DH_AUTOINCREMENT_ADDR BIT(7)
32 #define LIS2DH_SDO_PU_DISC_MASK BIT(7)
35 #define LIS2DH_ACCEL_X_EN_BIT BIT(0)
36 #define LIS2DH_ACCEL_Y_EN_BIT BIT(1)
37 #define LIS2DH_ACCEL_Z_EN_BIT BIT(2)
43 #define LIS2DH_LP_EN_BIT_MASK BIT(3)
45 #define LIS2DH_LP_EN_BIT BIT(3)
55 #define LIS2DH_ODR_4 4
82 #define LIS2DH_ODR_SHIFT 4
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/sensor/
Dapds9253.h5 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/dt-util.h>
19 #define APDS9253_RESOLUTION_19BIT_200MS BIT(4)
20 #define APDS9253_RESOLUTION_18BIT_100MS BIT(5) /* default */
21 #define APDS9253_RESOLUTION_17BIT_50MS (BIT(5) | BIT(4))
22 #define APDS9253_RESOLUTION_16BIT_25MS BIT(6)
23 #define APDS9253_RESOLUTION_13BIT_3MS (BIT(6) | BIT(4))
32 #define APDS9253_MEASUREMENT_RATE_2000MS (BIT(2) | BIT(1) | BIT(0))
33 #define APDS9253_MEASUREMENT_RATE_1000MS (BIT(2) | BIT(0))
34 #define APDS9253_MEASUREMENT_RATE_500MS BIT(2)
[all …]
/Zephyr-latest/dts/riscv/ite/
Dit8xxx2-wuc-map.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/dt-util.h>
11 it8xxx2-wuc-map {
12 compatible = "ite,it8xxx2-wuc-map";
16 wucs = <&wuc2 BIT(0)>; /* GPD0 */
19 wucs = <&wuc2 BIT(1)>; /* GPD1 */
22 wucs = <&wuc2 BIT(2)>; /* GPC4 */
25 wucs = <&wuc2 BIT(3)>; /* GPC6 */
28 wucs = <&wuc2 BIT(4)>; /* GPD2 */
31 wucs = <&wuc2 BIT(5)>; /* GPE4 */
[all …]
/Zephyr-latest/drivers/sensor/bosch/bmi160/
Dbmi160.h5 * SPDX-License-Identifier: Apache-2.0
113 /* Indicates a read operation; bit 7 is clear on write s*/
114 #define BMI160_REG_READ BIT(7)
120 #define BMI160_ERR_FATAL BIT(0)
121 #define BMI160_ERR_CODE BIT(1)
123 #define BMI160_ERR_I2C_FAIL BIT(5)
124 #define BMI160_ERR_DROP_CMD BIT(6)
125 #define BMI160_ERR_MAG_DRDY BIT(7)
132 #define BMI160_PMU_STATUS_ACC_POS 4
133 #define BMI160_PMU_STATUS_ACC_MASK (0x3 << 4)
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]

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