Lines Matching +full:4 +full:- +full:bit
4 * SPDX-License-Identifier: Apache-2.0
25 * 32-bit R/W
26 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
32 * 32-bit R/W
33 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
69 #define MCHP_BTMR_CTRL_SRESET_POS 4u
74 /** @brief Basic Timer(32 and 16 bit) registers. Total size = 20(0x14) bytes */
87 * Set count resolution in bit[0]
93 #define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS)
95 #define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS)
100 * Writing a non-zero value resets and start the counter counting down.
117 /* Control register at offset 0x00. Must use 32-bit access */
118 #define MCHP_CCT_CTRL_ACTIVATE BIT(0)
119 #define MCHP_CCT_CTRL_FRUN_EN BIT(1)
120 #define MCHP_CCT_CTRL_FRUN_RESET BIT(2) /* self clearing bit */
122 #define MCHP_CCT_CTRL_TCLK_MASK SHLU32(MCHP_CCT_CTRL_TCLK_MASK0, 4)
124 #define MCHP_CCT_CTRL_TCLK_DIV_2 SHLU32(1, 4)
125 #define MCHP_CCT_CTRL_TCLK_DIV_4 SHLU32(2, 4)
126 #define MCHP_CCT_CTRL_TCLK_DIV_8 SHLU32(3, 4)
127 #define MCHP_CCT_CTRL_TCLK_DIV_16 SHLU32(4, 4)
128 #define MCHP_CCT_CTRL_TCLK_DIV_32 SHLU32(5, 4)
129 #define MCHP_CCT_CTRL_TCLK_DIV_64 SHLU32(6, 4)
130 #define MCHP_CCT_CTRL_TCLK_DIV_128 SHLU32(7, 4)
131 #define MCHP_CCT_CTRL_COMP0_EN BIT(8)
132 #define MCHP_CCT_CTRL_COMP1_EN BIT(9)
133 #define MCHP_CCT_CTRL_COMP1_SET BIT(16) /* R/WS */
134 #define MCHP_CCT_CTRL_COMP0_SET BIT(17) /* R/WS */
135 #define MCHP_CCT_CTRL_COMP1_CLR BIT(24) /* R/W1C */
136 #define MCHP_CCT_CTRL_COMP0_CLR BIT(25) /* R/W1C */
159 #define MCHP_RTMR_CTRL_BLK_EN_MASK BIT(MCHP_RTMR_CTRL_BLK_EN_POS)
160 #define MCHP_RTMR_CTRL_BLK_EN BIT(MCHP_RTMR_CTRL_BLK_EN_POS)
163 #define MCHP_RTMR_CTRL_AUTO_RELOAD_MASK BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS)
164 #define MCHP_RTMR_CTRL_AUTO_RELOAD BIT(MCHP_RTMR_CTRL_AUTO_RELOAD_POS)
167 #define MCHP_RTMR_CTRL_START_MASK BIT(MCHP_RTMR_CTRL_START_POS)
168 #define MCHP_RTMR_CTRL_START BIT(MCHP_RTMR_CTRL_START_POS)
171 #define MCHP_RTMR_CTRL_HW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS)
172 #define MCHP_RTMR_CTRL_HW_HALT_EN BIT(MCHP_RTMR_CTRL_HW_HALT_EN_POS)
174 #define MCHP_RTMR_CTRL_FW_HALT_EN_POS 4u
175 #define MCHP_RTMR_CTRL_FW_HALT_EN_MASK BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS)
176 #define MCHP_RTMR_CTRL_FW_HALT_EN BIT(MCHP_RTMR_CTRL_FW_HALT_EN_POS)
189 #define MCHP_WKTMR_CTRL_WT_EN_MASK BIT(MCHP_WKTMR_CTRL_WT_EN_POS)
190 #define MCHP_WKTMR_CTRL_WT_EN BIT(MCHP_WKTMR_CTRL_WT_EN_POS)
192 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN_MASK BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)
193 #define MCHP_WKTMR_CTRL_PWRUP_EV_EN BIT(MCHP_WKTMR_CTRL_PWRUP_EV_EN_POS)
199 /* Sub-second interrupt select at +0x10 */
218 /* Sub-week control at +0x14 */
222 BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)
224 BIT(MCHP_WKTMR_SWKC_PWRUP_EV_STS_POS)
225 #define MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS 4
227 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)
229 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_STS_POS)
232 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)
234 BIT(MCHP_WKTMR_SWKC_SYSPWR_PRES_EN_POS)
237 BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)
239 BIT(MCHP_WKTMR_SWKC_AUTO_RELOAD_POS)
241 /* Sub-week alarm counter at +0x18 */
253 #define MCHP_WKTMR_BGPO_0_PWR_RO BIT(0)
257 #define MCHP_WKTMR_BGPO_RST_VBAT(n) BIT(n)