Lines Matching +full:4 +full:- +full:bit

4  * SPDX-License-Identifier: Apache-2.0
12 #define BQ24190_REG_ISC_EN_HIZ_MASK  BIT(7)
18 /* Power-On Configuration */
20 #define BQ24190_REG_POC_RESET_MASK         BIT(7)
23 #define BQ24190_REG_POC_WDT_RESET_MASK     BIT(6)
25 #define BQ24190_REG_POC_CHG_CONFIG_MASK    GENMASK(5, 4)
26 #define BQ24190_REG_POC_CHG_CONFIG_SHIFT   4
35 #define BQ24190_REG_POC_BOOST_LIM_MASK     BIT(0)
46 #define BQ24190_REG_CCC_FORCE_20PCT_MASK  BIT(0)
49 /* Pre-charge/Termination Current Cntl */
51 #define BQ24190_REG_PCTCC_IPRECHG_MASK      GENMASK(7, 4)
52 #define BQ24190_REG_PCTCC_IPRECHG_SHIFT     4
72 #define BQ24190_REG_CVC_BATLOWV_MASK   BIT(1)
74 #define BQ24190_REG_CVC_VRECHG_MASK    BIT(0)
79 #define BQ24190_REG_CTTC_EN_TERM_MASK     BIT(7)
81 #define BQ24190_REG_CTTC_TERM_STAT_MASK   BIT(6)
83 #define BQ24190_REG_CTTC_WATCHDOG_MASK    GENMASK(5, 4)
84 #define BQ24190_REG_CTTC_WATCHDOG_SHIFT   4
85 #define BQ24190_REG_CTTC_EN_TIMER_MASK    BIT(3)
89 #define BQ24190_REG_CTTC_JEITA_ISET_MASK  BIT(0)
96 #define BQ24190_REG_ICTRC_VCLAMP_MASK    GENMASK(4, 2)
103 #define BQ24190_REG_MOC_DPDM_EN_MASK         BIT(7)
105 #define BQ24190_REG_MOC_TMR2X_EN_MASK        BIT(6)
107 #define BQ24190_REG_MOC_BATFET_DISABLE_MASK  BIT(5)
109 #define BQ24190_REG_MOC_JEITA_VSET_MASK      BIT(4)
110 #define BQ24190_REG_MOC_JEITA_VSET_SHIFT     4
118 #define BQ24190_REG_SS_CHRG_STAT_MASK   GENMASK(5, 4)
119 #define BQ24190_REG_SS_CHRG_STAT_SHIFT  4
124 #define BQ24190_REG_SS_DPM_STAT_MASK    BIT(3)
126 #define BQ24190_REG_SS_PG_STAT_MASK     BIT(2)
128 #define BQ24190_REG_SS_THERM_STAT_MASK  BIT(1)
130 #define BQ24190_REG_SS_VSYS_STAT_MASK   BIT(0)
135 #define BQ24190_REG_F_WATCHDOG_FAULT_MASK  BIT(7)
137 #define BQ24190_REG_F_BOOST_FAULT_MASK     BIT(6)
139 #define BQ24190_REG_F_CHRG_FAULT_MASK      GENMASK(5, 4)
140 #define BQ24190_REG_F_CHRG_FAULT_SHIFT     4
144 #define BQ24190_REG_F_BAT_FAULT_MASK       BIT(3)
162 #define BQ24190_REG_VPRS_TS_PROFILE_MASK  BIT(2)