Searched +full:32 +full:mb (Results 1 – 25 of 187) sorted by relevance
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| /Zephyr-latest/soc/espressif/common/ |
| D | Kconfig.esptool | 140 bool "1 MB"
142 bool "2 MB"
144 bool "4 MB"
146 bool "8 MB"
148 bool "16 MB"
150 bool "32 MB"
152 bool "64 MB"
154 bool "128 MB"
159 default "1MB" if ESPTOOLPY_FLASHSIZE_1MB
160 default "2MB" if ESPTOOLPY_FLASHSIZE_2MB
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| /Zephyr-latest/dts/xtensa/ |
| D | dc233c.dtsi | 22 * Although RAM is of size 128MB (0x08000000), limit this to 16MB so
32 * Although ROM is of size 32MB (0x02000000), limit this to 16KB so
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| /Zephyr-latest/include/zephyr/arch/arm/mpu/ |
| D | arm_mpu_v7m.h | 83 #define REGION_32B REGION_SIZE(32B)
93 #define REGION_32K REGION_SIZE(32KB)
98 #define REGION_1M REGION_SIZE(1MB)
99 #define REGION_2M REGION_SIZE(2MB)
100 #define REGION_4M REGION_SIZE(4MB)
101 #define REGION_8M REGION_SIZE(8MB)
102 #define REGION_16M REGION_SIZE(16MB)
103 #define REGION_32M REGION_SIZE(32MB)
104 #define REGION_64M REGION_SIZE(64MB)
105 #define REGION_128M REGION_SIZE(128MB)
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| /Zephyr-latest/lib/acpi/ |
| D | Kconfig | 29 def_int 1048576 # 1MB
45 default 32
51 default 32
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| /Zephyr-latest/samples/drivers/virtualization/ivshmem/doorbell/boards/ |
| D | qemu_cortex_a53.conf | 7 # Hungry PCI requires phys addresses with more than 32 bits
19 # The default ivshmem memory size is 4MB (4194304), but libc uses the arena as well
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| D | qemu_kvm_arm64.conf | 7 # Hungry PCI requires phys addresses with more than 32 bits
19 # The default ivshmem memory size is 4MB (4194304), but libc uses the arena as well
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| /Zephyr-latest/arch/arm/core/mmu/ |
| D | arm_mmu.c | 5 * table format. The standard page size is 4 kB, 1 MB sections
44 * each table covers a range of 1 MB, the number of L2 tables
51 * if the respective table is in use, if so, to which 1 MB
133 * a page is to be mapped in a 1 MB virtual address range that
136 * @param va 32-bit virtual address to be mapped.
137 * @retval pointer to the L2 table now assigned to the 1 MB
157 * which 1 MB virtual address range it is being assigned to. in arm_mmu_assign_l2_table()
187 * 1 MB virtual address range. This function is called whenever
383 * @brief Maps a 1 MB memory range via a level 1 page table entry
384 * Maps a 1 MB memory range using a level 1 page table entry of type
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| /Zephyr-latest/soc/cdns/dc233c/ |
| D | mmu.c | 23 /* The ROM is 32MB but the address wraps around back to 0x00000000.
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| /Zephyr-latest/dts/common/espressif/ |
| D | partitions_0x0_default_32M.dtsi | 7 /* 32MB flash partition table */
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| D | partitions_0x1000_default_32M.dtsi | 7 /* 32MB flash partition table */
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| D | partitions_0x0_amp_32M.dtsi | 7 /* 32MB flash partition table */
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| D | partitions_0x1000_amp_32M.dtsi | 7 /* 32MB flash partition table */
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| /Zephyr-latest/samples/subsys/display/lvgl/ |
| D | sample.yaml | 10 # ~25K seem to be sufficient for most cases, rounded to 32K.
12 min_ram: 32
27 # The minimum RAM needed for this display is actually around 8MB,
29 min_ram: 32
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| /Zephyr-latest/arch/x86/include/ |
| D | kernel_arch_data.h | 11 * for Intel; vectors 32 to 255 are user defined interrupt vectors.
37 #define IV_IRQS 32 /* start of vectors available for IRQs */
56 #define CR4_PSE BIT(4) /* Page size extension (4MB pages) */
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| /Zephyr-latest/boards/renesas/ek_ra6m4/doc/ |
| D | index.rst | 26 providing precision 24.000 MHz and 32,768 Hz reference clock.
64 - 32 Mb (256 Mb) External Quad-SPI Flash
65 - 64 Mb (512 Mb) External Octo-SPI Flash
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| /Zephyr-latest/boards/renesas/ek_ra6m5/doc/ |
| D | index.rst | 22 providing precision 24.000 MHz and 32,768 Hz reference clock.
61 - 32 Mb (256 Mb) External Quad-SPI Flash
62 - 64 Mb (512 Mb) External Octo-SPI Flash
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| /Zephyr-latest/drivers/dma/ |
| D | dma_pl330.h | 14 * Max burst length and max burst size for 32bit system with
31 * b101 = 32 bytes
40 * PL330 has 32bit registers for source and destination addresses
44 /* PL330 supports max 16MB dma based on AXI bus size */
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| /Zephyr-latest/boards/renesas/ek_ra4m3/doc/ |
| D | index.rst | 9 The Renesas RA4M3 group of 32-bit microcontrollers (MCUs) uses the high-performance
24 - 1 MB Code Flash, 128 KB SRAM
29 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to…
64 - 32 MB (256 Mb) External Quad-SPI Flash
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| /Zephyr-latest/boards/espressif/esp8684_devkitm/doc/ |
| D | index.rst | 7 module with 1 MB/2 MB/4 MB SPI flash. This board integrates complete Wi-Fi and Bluetooth LE functio…
15 32-bit, single-core processor, with 272 KB of SRAM (16 KB dedicated to cache) and 576 KB of ROM.
23 - 32-bit core RISC-V microcontroller with a maximum clock speed of 120 MHz
24 - 2 MB or 4 MB in chip (ESP8684) or in package (ESP32-C2) flash
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| /Zephyr-latest/dts/bindings/memory-controllers/ |
| D | renesas,smartbond-nor-psram.yaml | 117 - "addr-range-32bit"
120 Address size to use in auto mode. In 24-bit mode up to 16MB can be
121 accessed whilst in 32-bit mode up to 32MB can be accessed which is
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| /Zephyr-latest/drivers/pcie/host/ |
| D | Kconfig | 36 from memory space into any 256 MB region of the PCIe configuration space.
53 MSI can support up to 32 different messages. This will enable the
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| /Zephyr-latest/samples/subsys/zbus/benchmark/ |
| D | README.rst | 37 I: Average data rate: 12.62MB/s
52 | LIS/SUB/MSG_SUB | 1,4,8 | 2,8,32,128,512 | float | int | …
67 LISTENERS,1,32,74513.0,9277,23151
72 LISTENERS,4,32,24057.333333333332,9304,23202
77 LISTENERS,8,32,15635.0,9340,23270
82 SUBSCRIBERS,1,32,514139.3333333333,9957,23523
87 SUBSCRIBERS,4,32,354583.3333333333,12024,24194
92 SUBSCRIBERS,8,32,332804.0,14780,24926
97 MSG_SUBSCRIBERS,1,32,610168.0,10401,25675
102 MSG_SUBSCRIBERS,4,32,396127.6666666667,12348,26186
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| /Zephyr-latest/boards/adi/max32690fthr/doc/ |
| D | index.rst | 22 - External Crystal Support (32MHz required for BLE)
25 - 3MB Internal Flash, 1MB Internal SRAM (832kB ECC ON)
32 - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload
51 - Up To Six 32-Bit Timers with 8mA High Drive
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| /Zephyr-latest/boards/beagle/beaglebone_ai64/doc/ |
| D | index.rst | 27 32-bit input address into a 48-bit output address. Any input transaction that
77 | ATCM | 0x05c00000 | 0x05d00000 | 0x05e00000 | 0x05f00000 | 32KB |
79 | BTCM | 0x05c10000 | 0x05d10000 | 0x05e10000 | 0x05f00000 | 32KB |
81 | DDR0 | 0xA2000000 | 0xA3000000 | 0xA4000000 | 0xA5000000 | 1MB |
83 | DDR1 | 0xA2100000 | 0xA3000000 | 0xA4100000 | 0xA5000000 | 15MB |
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| /Zephyr-latest/boards/arm/mps2/doc/ |
| D | mps2_an521.rst | 57 The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory
63 the offset value is the offset from the base of the 4MB code or SRAM block,
69 | mps2/an521/cpu0 | 0 | 4MB (0) | 4MB (0) | S |
71 | mps2/an521/cpu0/ns | 0 | 512KB (1MB) | 512KB (1MB) | NS |
73 | mps2/an521/cpu1 | 1 | 468KB (3628KB) | 512KB (1.5MB) | NS |
81 in a starting address of 0x00100000. SRAM begins with a 1MB offset at
85 AN521, using the final 468KB code memory in the 4MB code block. This value
88 3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB
109 - 4MB of code memory (SSRAM1)
110 - 4MB of SRAM (SSRAM2 and SSRAM3)
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