Lines Matching +full:32 +full:mb

57 The AN521 has 4MB allocated for code space, and 4MB for SRAM. These memory
63 the offset value is the offset from the base of the 4MB code or SRAM block,
69 | mps2/an521/cpu0         | 0   | 4MB (0)        | 4MB (0)        | S          |
71 | mps2/an521/cpu0/ns      | 0   | 512KB (1MB)    | 512KB (1MB)    | NS         |
73 | mps2/an521/cpu1         | 1   | 468KB (3628KB) | 512KB (1.5MB)  | NS         |
81 in a starting address of 0x00100000. SRAM begins with a 1MB offset at
85 AN521, using the final 468KB code memory in the 4MB code block. This value
88 3628KB (address 0x0038B000), and sram starts with an offset of 1.5MB
109   - 4MB of code memory (SSRAM1)
110   - 4MB of SRAM (SSRAM2 and SSRAM3)
111   - 16MB of parallel SRAM (PSRAM, non-secure only)
253 - Pins 32 -  47 are for GPIO2
352    - S32KCLK : 32kHz
530 2. Open ``<MPS2 device name>/MB/HBI0263C/AN521/images.txt``.
538    TOTALIMAGES: 1 ;Number of Images (Max: 32)