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/Zephyr-Core-3.6.0/dts/arm/atmel/
Dsamr21.dtsi27 #dma-cells = <2>;
37 #gpio-cells = <2>;
38 #atmel,pin-cells = <2>;
51 clocks = <&gclk 26>, <&pm 0x20 8>;
62 clocks = <&gclk 26>, <&pm 0x20 9>;
65 channels = <2>;
73 clocks = <&gclk 27>, <&pm 0x20 10>;
76 channels = <2>;
84 clocks = <&gclk 0x14>, <&pm 0x20 2>;
90 clocks = <&gclk 0x15>, <&pm 0x20 3>;
[all …]
Dsamd21.dtsi27 #dma-cells = <2>;
32 reg = <0x42003800 0x20>;
34 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
42 clocks = <&gclk 26>, <&pm 0x20 8>;
53 clocks = <&gclk 26>, <&pm 0x20 9>;
56 channels = <2>;
64 clocks = <&gclk 27>, <&pm 0x20 10>;
67 channels = <2>;
75 clocks = <&gclk 33>, <&pm 0x20 18>;
81 clocks = <&gclk 0x14>, <&pm 0x20 2>;
[all …]
Dsamd20.dtsi12 tc-2 = &tc2;
19 reg = <0x42002000 0x20>;
21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
27 reg = <0x42002800 0x20>;
29 clocks = <&gclk 0x14>, <&pm 0x20 10>;
35 reg = <0x42003800 0x20>;
37 clocks = <&gclk 0x16>, <&pm 0x20 14>;
45 clocks = <&gclk 26>, <&pm 0x20 18>;
51 clocks = <&gclk 0xd>, <&pm 0x20 2>;
57 clocks = <&gclk 0xe>, <&pm 0x20 3>;
[all …]
Dsaml21.dtsi23 #dma-cells = <2>;
55 channels = <2>;
81 clocks = <&gclk 20>, <&mclk 0x1c 2>;
99 clocks = <&gclk 24>, <&mclk 0x20 1>;
105 clocks = <&gclk 29>, <&mclk 0x20 2>;
112 clocks = <&gclk 30>, <&mclk 0x20 3>;
Dsamd5x.dtsi47 sercom-2 = &sercom2;
55 tc-2 = &tc2;
61 tcc-2 = &tcc2;
94 #clock-cells = <2>;
122 #dma-cells = <2>;
201 clocks = <&gclk 34>, <&mclk 0x20 0>;
210 clocks = <&gclk 35>, <&mclk 0x20 1>;
219 clocks = <&gclk 36>, <&mclk 0x20 2>;
228 clocks = <&gclk 37>, <&mclk 0x20 3>;
242 #gpio-cells = <2>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/xilinx/
Dzynqmp_rpu.dtsi37 reg = <0xff990200 0x20>,
38 <0xff990220 0x20>,
39 <0xff990040 0x20>,
40 <0xff990060 0x20>;
48 remote-ipi-id = <2>;
49 reg = <0xff990260 0x20>,
50 <0xff990280 0x20>,
51 <0xff990420 0x20>,
52 <0xff990440 0x20>;
66 local-ipi-id = <2>;
[all …]
/Zephyr-Core-3.6.0/dts/arm/renesas/ra/
Dra4-cm4-common.dtsi13 reg = <0x400400c0 0x20>;
15 #gpio-cells = <2>;
22 reg = <0x400400e0 0x20>;
24 #gpio-cells = <2>;
31 reg = <0x40040100 0x20>;
33 #gpio-cells = <2>;
40 reg = <0x40040120 0x20>;
42 #gpio-cells = <2>;
49 reg = <0x40070040 0x20>;
56 clocks = <&cgc RA_CLOCK_SCI(2)>;
Dra-cm4-common.dtsi64 clock-div = <2>;
121 reg = <0x40040000 0x20>;
123 #gpio-cells = <2>;
133 port-irq2-pins = <2>;
144 reg = <0x40040020 0x20>;
146 #gpio-cells = <2>;
165 reg = <0x40040040 0x20>;
167 #gpio-cells = <2>;
185 reg = <0x40040060 0x20>;
187 #gpio-cells = <2>;
[all …]
/Zephyr-Core-3.6.0/tests/net/ppp/driver/src/
Dmain.c50 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
51 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
52 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
66 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
67 0x7d, 0x26, 0x7d, 0x20, 0x7d, 0x20, 0x7d, 0x20,
68 0x7d, 0x20, 0x7d, 0x25, 0x7d, 0x26, 0x5d, 0x58,
73 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
79 0x7d, 0x21, 0x7d, 0x20, 0x7d, 0x24, 0x1c, 0x90, 0x7e
89 0x21, 0x7d, 0x22, 0x7d, 0x21, 0x7d, 0x20, 0x7d,
102 0x7d, 0x23, 0x7d, 0x20, 0x7d, 0x34, 0x7d, 0x22,
[all …]
/Zephyr-Core-3.6.0/dts/arm/microchip/
Dmec1501hsz.dtsi53 i2c-smb-2 = &i2c_smb_2;
88 sources = <0 1 2 4 5 10 16 17>;
102 interrupts = <3 2>;
106 #gpio-cells=<2>;
112 interrupts = <2 2>;
116 #gpio-cells=<2>;
123 interrupts = <1 2>;
124 port-id = <2>;
126 #gpio-cells=<2>;
133 interrupts = <0 2>;
[all …]
Dmec172x_common.dtsi42 sources = <0 1 2 3 4 5 6 7
53 sources = <0 1 2 3 4 5 6 7
62 interrupts = <2 0>;
63 girq-id = <2>;
64 sources = <0 1 2 3 4 5 6 7
75 sources = <0 1 2 3 4 5 6 7
86 sources = <0 1 2 3 4 5 6 7
97 sources = <0 1 2 3 4>;
105 sources = <0 1 2 3 4 5 6 7
114 sources = <0 1 2 3 4 5 6 7
[all …]
Dmec172xnlj.dtsi62 interrupts = <155 2>;
71 reg = <0x40005890 0x20>;
79 reg = <0x400058a0 0x20>;
87 reg = <0x400058b0 0x20>;
/Zephyr-Core-3.6.0/tests/kconfig/configdefault/
DKconfig30 bool "SYM Y 2"
36 bool "SYM N 2"
219 int "Int 2"
220 default 2
233 default 2
243 default 2
247 default 0x20
250 hex "Hex 0x20"
257 string "Hex 0x20"
/Zephyr-Core-3.6.0/drivers/sensor/icm42605/
Dicm42605_reg.h18 #define REG_ACCEL_DATA_X0 0x20
92 /* BANK 2 */
148 #define BIT_TEMP_FILT_BW_170 0x20
176 #define SHIFT_INT1_MODE 2
179 #define BIT_TEMP_DIS 0x20
195 #define BIT_DMP_MEM_RESET_EN 0x20
200 #define BIT_COUNT_BIG_ENDIAN 0x20
224 #define BIT_FIFO_WM_TH 0x20
236 #define BIT_INT_PLL_RDY_INT1_EN 0x20
255 #define BIT_TEST_AZ_EN 0x20
[all …]
/Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/npcx9/
Dnpcx9-miwus-int-map.dtsi20 irq-prio = <2>;
25 irq-prio = <2>;
30 irq-prio = <2>;
35 irq-prio = <2>;
36 group-mask = <0x20>;
40 irq-prio = <2>;
45 irq-prio = <2>;
56 irq-prio = <2>;
57 group-mask = <0x20>;
61 irq-prio = <2>;
/Zephyr-Core-3.6.0/dts/arm/nuvoton/npcx/npcx4/
Dnpcx4-miwus-int-map.dtsi20 irq-prio = <2>;
25 irq-prio = <2>;
30 irq-prio = <2>;
35 irq-prio = <2>;
36 group-mask = <0x20>;
40 irq-prio = <2>;
45 irq-prio = <2>;
56 irq-prio = <2>;
61 irq-prio = <2>;
62 group-mask = <0x20>;
[all …]
/Zephyr-Core-3.6.0/tests/drivers/interrupt_controller/intc_plic/src/
Dmain.c19 zassert_equal(1, local_irq_to_reg_index(0x20)); in ZTEST()
21 zassert_equal(2, local_irq_to_reg_index(0x40)); in ZTEST()
28 zassert_equal(4, local_irq_to_reg_offset(0x20)); in ZTEST()
/Zephyr-Core-3.6.0/dts/riscv/ite/
Dit81xx2.dtsi26 #gpio-cells = <2>;
39 #gpio-cells = <2>;
52 #gpio-cells = <2>;
76 0x1 0x02 0x20 0x40 >;
77 #pinmux-cells = <2>;
96 #pinmux-cells = <2>;
113 volt-sel-mask = <0x80 0x20 0x10 0
115 #pinmux-cells = <2>;
133 0x40 0x10 0x20 0x40 >;
134 #pinmux-cells = <2>;
[all …]
/Zephyr-Core-3.6.0/tests/subsys/modem/modem_ppp/src/
Dmain.c43 0x21, 0x7D, 0x20, 0x7D, 0x24, 0xD1, 0xB5, 0x7E};
48 0x7E, 0xFF, 0x7D, 0x23, 0x7D, 0x20, 0x21, 0x45, 0x7D, 0x20, 0x7D, 0x20, 0x29, 0x87, 0x6E,
49 0x40, 0x7D, 0x20, 0xE8, 0x7D, 0x31, 0xC1, 0xE9, 0x7D, 0x23, 0xFB, 0x7D, 0x25, 0x20, 0x7D,
50 0x2A, 0x2B, 0x36, 0x26, 0x25, 0x7D, 0x32, 0x8C, 0x3E, 0x7D, 0x20, 0x7D, 0x35, 0xBD, 0xF3,
51 0x2D, 0x7D, 0x20, 0x7D, 0x2B, 0x7D, 0x20, 0x7D, 0x27, 0x7D, 0x20, 0x7D, 0x24, 0x7D, 0x20,
52 0x7D, 0x24, 0x7D, 0x2A, 0x7D, 0x20, 0x7D, 0x2A, 0x7D, 0x20, 0xD4, 0x31, 0x7E};
56 0x05, 0x20, 0x0A, 0x2B, 0x36, 0x26, 0x25, 0x12, 0x8C, 0x3E, 0x00, 0x15, 0xBD, 0xF3,
61 0xFB, 0x05, 0x20, 0x0A, 0x2B, 0x36, 0x26, 0x25, 0x12, 0x8C, 0x3E, 0x00, 0x15, 0xBD, 0xF3,
66 0x20, 0x7D, 0x24, 0xD1, 0xB5, 0x7E};
178 unwrapped[unwrapped_pos] = wrapped[wrapped_pos + 1] ^ 0x20; in test_modem_ppp_unwrap()
[all …]
/Zephyr-Core-3.6.0/drivers/usb/common/
Dusb_dwc2_hw.h205 #define USB_DWC2_GINTSTS_OTGINT_POS 2UL
213 #define USB_DWC2_GRXSTSR_PKTSTS_OUT_DATA 2
257 #define USB_DWC2_GHWCFG1_EPDIR_POS(i) (i * 2)
259 #define USB_DWC2_GHWCFG1_EPDIR_OUT 2
274 #define USB_DWC2_GHWCFG2_FSPHYTYPE_FSPLUSUTMI 2
280 #define USB_DWC2_GHWCFG2_HSPHYTYPE_ULPI 2
285 #define USB_DWC2_GHWCFG2_OTGARCH_INTERNALDMA 2
294 #define USB_DWC2_GHWCFG2_OTGMODE_NHNPNSRP 2
322 #define USB_DWC2_GHWCFG3_PKTSIZEWIDTH_BITS6 2U
333 #define USB_DWC2_GHWCFG3_XFERSIZEWIDTH_WIDTH13 2U
[all …]
/Zephyr-Core-3.6.0/tests/crypto/tinycrypt/src/
Dhmac.c76 0x48, 0x69, 0x20, 0x54, 0x68, 0x65, 0x72, 0x65 in ZTEST()
105 0x77, 0x68, 0x61, 0x74, 0x20, 0x64, 0x6f, 0x20, 0x79, 0x61, in ZTEST()
106 0x20, 0x77, in ZTEST()
107 0x61, 0x6e, 0x74, 0x20, 0x66, 0x6f, 0x72, 0x20, 0x6e, 0x6f, in ZTEST()
123 result = do_hmac_test(&h, 2, data, sizeof(data), in ZTEST()
223 0x54, 0x65, 0x73, 0x74, 0x20, 0x57, 0x69, 0x74, 0x68, 0x20, in ZTEST()
232 0x93, 0xf8, 0x60, 0xaa, 0xb0, 0xcd, 0x20, 0xc5 in ZTEST()
275 0x54, 0x65, 0x73, 0x74, 0x20, 0x55, 0x73, 0x69, 0x6e, 0x67, in ZTEST()
276 0x20, 0x4c, in ZTEST()
277 0x61, 0x72, 0x67, 0x65, 0x72, 0x20, 0x54, 0x68, 0x61, 0x6e, in ZTEST()
[all …]
/Zephyr-Core-3.6.0/tests/drivers/build_all/pwm/
Dmax31790.overlay13 reg = <0x20>;
15 #pwm-cells = <2>;
/Zephyr-Core-3.6.0/drivers/sensor/bmp581/
Dbmp581.h62 #define BMP5_REG_PRESS_DATA_XLSB 0x20
92 #define BMP5_NVM_START_ADDR 0x20
157 #define BMP5_INT_OD_POS 2
168 #define BMP5_INT_FIFO_THRES_EN_POS 2
175 #define BMP5_ODR_POS 2
199 #define BMP5_SHDW_SET_IIR_PRESS_MSK 0x20
209 #define BMP5_IIR_FLUSH_FORCED_EN_POS 2
229 #define BMP5_FIFO_MODE_MSK 0x20
233 #define BMP5_FIFO_DEC_SEL_POS 2
/Zephyr-Core-3.6.0/include/zephyr/arch/nios2/
Dlinker.ld37 * with the exception vector 0x20 bytes after it.
38 * 2. XIP systems where the reset vector is at the beginning of ROM and
61 RESET (rx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20
62 FLASH (rx) : ORIGIN = _RESET_VECTOR + 0x20 , LENGTH = (_ROM_SIZE - 0x20 - ROM_END_OFFSET)
65 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
73 RESET (wx) : ORIGIN = _RESET_VECTOR, LENGTH = 0x20
77 IDT_LIST (wx) : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
/Zephyr-Core-3.6.0/dts/bindings/gpio/
Draspberrypi-40pins-header.yaml7 The Raspberry Pi layout provides a 2x20 pins header.
14 2 GPIO4 GPIO14/UART0_TXD 3

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