1/*
2 * Copyright (c) 2021 Argentum Systems Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <atmel/saml2x.dtsi>
8
9/ {
10	soc {
11		usb0: usb@41000000 {
12			compatible = "atmel,sam0-usb";
13			status = "disabled";
14			reg = <0x41000000 0x1000>;
15			interrupts = <6 0>;
16			num-bidir-endpoints = <8>;
17		};
18
19		dmac: dmac@44000400 {
20			compatible = "atmel,sam0-dmac";
21			reg = <0x44000400 0x50>;
22			interrupts = <5 0>;
23			#dma-cells = <2>;
24		};
25
26		tcc0: tcc@42001400 {
27			compatible = "atmel,sam0-tcc";
28			reg = <0x42001400 0x80>;
29			interrupts = <14 0>;
30			clocks = <&gclk 25>, <&mclk 0x1c 5>;
31			clock-names = "GCLK", "MCLK";
32
33			channels = <4>;
34			counter-size = <24>;
35		};
36
37		tcc1: tcc@42001800 {
38			compatible = "atmel,sam0-tcc";
39			reg = <0x42001800 0x80>;
40			interrupts = <15 0>;
41			clocks = <&gclk 25>, <&mclk 0x1c 6>;
42			clock-names = "GCLK", "MCLK";
43
44			channels = <4>;
45			counter-size = <24>;
46		};
47
48		tcc2: tcc@42001c00 {
49			compatible = "atmel,sam0-tcc";
50			reg = <0x42001C00 0x80>;
51			interrupts = <16 0>;
52			clocks = <&gclk 26>, <&mclk 0x1c 7>;
53			clock-names = "GCLK", "MCLK";
54
55			channels = <2>;
56			counter-size = <16>;
57		};
58	};
59};
60
61&dac {
62	interrupts = <24 0>;
63	clocks = <&gclk 32>, <&mclk 0x1c 12>;
64	clock-names = "GCLK", "MCLK";
65};
66
67&sercom0 {
68	interrupts = <8 0>;
69	clocks = <&gclk 18>, <&mclk 0x1c 0>;
70	clock-names = "GCLK", "MCLK";
71};
72
73&sercom1 {
74	interrupts = <9 0>;
75	clocks = <&gclk 19>, <&mclk 0x1c 1>;
76	clock-names = "GCLK", "MCLK";
77};
78
79&sercom2 {
80	interrupts = <10 0>;
81	clocks = <&gclk 20>, <&mclk 0x1c 2>;
82	clock-names = "GCLK", "MCLK";
83};
84
85&sercom3 {
86	interrupts = <11 0>;
87	clocks = <&gclk 21>, <&mclk 0x1c 3>;
88	clock-names = "GCLK", "MCLK";
89};
90
91&sercom4 {
92	interrupts = <12 0>;
93	clocks = <&gclk 22>, <&mclk 0x1c 4>;
94	clock-names = "GCLK", "MCLK";
95};
96
97&sercom5 {
98	interrupts = <13 0>;
99	clocks = <&gclk 24>, <&mclk 0x20 1>;
100	clock-names = "GCLK", "MCLK";
101};
102
103&tc4 {
104	interrupts = <21 0>;
105	clocks = <&gclk 29>, <&mclk 0x20 2>;
106	clock-names = "GCLK", "MCLK";
107};
108
109&adc {
110	interrupts = <22 0>;
111	interrupt-names = "resrdy";
112	clocks = <&gclk 30>, <&mclk 0x20 3>;
113	clock-names = "GCLK", "MCLK";
114};
115