1/*
2 * Copyright (c) 2019 ML!PA Consulting GmbH
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <arm/armv7-m.dtsi>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/pwm/pwm.h>
12
13/ {
14	chosen {
15		zephyr,flash-controller = &nvmctrl;
16	};
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu0: cpu@0 {
23			device_type = "cpu";
24			compatible = "arm,cortex-m4f";
25			reg = <0>;
26			#address-cells = <1>;
27			#size-cells = <1>;
28
29			mpu: mpu@e000ed90 {
30				compatible = "arm,armv7m-mpu";
31				reg = <0xe000ed90 0x40>;
32			};
33		};
34	};
35
36	aliases {
37		adc-0 = &adc0;
38		adc-1 = &adc1;
39
40		port-a = &porta;
41		port-b = &portb;
42		port-c = &portc;
43		port-d = &portd;
44
45		sercom-0 = &sercom0;
46		sercom-1 = &sercom1;
47		sercom-2 = &sercom2;
48		sercom-3 = &sercom3;
49		sercom-4 = &sercom4;
50		sercom-5 = &sercom5;
51		sercom-6 = &sercom6;
52		sercom-7 = &sercom7;
53
54		tc-0 = &tc0;
55		tc-2 = &tc2;
56		tc-4 = &tc4;
57		tc-6 = &tc6;
58
59		tcc-0 = &tcc0;
60		tcc-1 = &tcc1;
61		tcc-2 = &tcc2;
62		tcc-3 = &tcc3;
63		tcc-4 = &tcc4;
64
65		watchdog0 = &wdog;
66	};
67
68	chosen {
69		zephyr,entropy = &trng;
70	};
71
72	soc {
73		sram0: memory@20000000 {
74			compatible = "mmio-sram";
75			reg = <0x20000000 0x40000>;
76		};
77
78		backup0: memory@47000000 {
79			compatible = "mmio-sram";
80			reg = <0x47000000 0x2000>;
81		};
82
83		id: device_id@8061fc {
84			compatible = "atmel,sam0-id";
85			reg =	<0x008061FC 0x4>,
86				<0x00806010 0x4>,
87				<0x00806014 0x4>,
88				<0x00806018 0x4>;
89		};
90
91		mclk: mclk@40000800 {
92			compatible = "atmel,samd5x-mclk";
93			reg = <0x40000800 0x400>;
94			#clock-cells = <2>;
95		};
96
97		gclk: gclk@40001c00 {
98			compatible = "atmel,samd5x-gclk";
99			reg = <0x40001c00 0x400>;
100			#clock-cells = <1>;
101		};
102
103		nvmctrl: nvmctrl@41004000  {
104			compatible = "atmel,sam0-nvmctrl";
105			reg = <0x41004000 0x22>;
106			interrupts = <29 0>, <30 0>;
107			lock-regions = <32>;
108
109			#address-cells = <1>;
110			#size-cells = <1>;
111
112			flash0: flash@0 {
113				compatible = "soc-nv-flash";
114				write-block-size = <8>;
115			};
116		};
117
118		dmac: dmac@4100a000 {
119			compatible = "atmel,sam0-dmac";
120			reg = <0x4100A000 0x50>;
121			interrupts = <31 0>, <32 0>, <33 0>, <34 0>, <35 0>;
122			#dma-cells = <2>;
123		};
124
125		eic: eic@40002800 {
126			compatible = "atmel,sam0-eic";
127			reg = <0x40002800 0x38>;
128			interrupts = <12 0>, <13 0>, <14 0>, <15 0>,
129				     <16 0>, <17 0>, <18 0>, <19 0>,
130				     <20 0>, <21 0>, <22 0>, <23 0>,
131				     <24 0>, <25 0>, <26 0>, <27 0>;
132		};
133
134		pinmux_a: pinmux@41008000 {
135			compatible = "atmel,sam0-pinmux";
136			reg = <0x41008000 0x80>;
137		};
138
139		pinmux_b: pinmux@41008080 {
140			compatible = "atmel,sam0-pinmux";
141			reg = <0x41008080 0x80>;
142		};
143
144		pinmux_c: pinmux@41008100 {
145			compatible = "atmel,sam0-pinmux";
146			reg = <0x41008100 0x80>;
147		};
148
149		pinmux_d: pinmux@41008180 {
150			compatible = "atmel,sam0-pinmux";
151			reg = <0x41008180 0x80>;
152		};
153
154		wdog: watchdog@40002000 {
155			compatible = "atmel,sam0-watchdog";
156			reg = <0x40002000 13>;
157			interrupts = <10 0>;
158		};
159
160		sercom0: sercom@40003000 {
161			compatible = "atmel,sam0-sercom";
162			reg = <0x40003000 0x40>;
163			interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
164			status = "disabled";
165			clocks = <&gclk 7>, <&mclk 0x14 12>;
166			clock-names = "GCLK", "MCLK";
167		};
168
169		sercom1: sercom@40003400 {
170			compatible = "atmel,sam0-sercom";
171			reg = <0x40003400 0x40>;
172			interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
173			status = "disabled";
174			clocks = <&gclk 8>, <&mclk 0x14 13>;
175			clock-names = "GCLK", "MCLK";
176		};
177
178		sercom2: sercom@41012000 {
179			compatible = "atmel,sam0-sercom";
180			reg = <0x41012000 0x40>;
181			interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
182			status = "disabled";
183			clocks = <&gclk 23>, <&mclk 0x18 9>;
184			clock-names = "GCLK", "MCLK";
185		};
186
187		sercom3: sercom@41014000 {
188			compatible = "atmel,sam0-sercom";
189			reg = <0x41014000 0x40>;
190			interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
191			status = "disabled";
192			clocks = <&gclk 24>, <&mclk 0x18 10>;
193			clock-names = "GCLK", "MCLK";
194		};
195
196		sercom4: sercom@43000000 {
197			compatible = "atmel,sam0-sercom";
198			reg = <0x43000000 0x40>;
199			interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
200			status = "disabled";
201			clocks = <&gclk 34>, <&mclk 0x20 0>;
202			clock-names = "GCLK", "MCLK";
203		};
204
205		sercom5: sercom@43000400 {
206			compatible = "atmel,sam0-sercom";
207			reg = <0x43000400 0x40>;
208			interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
209			status = "disabled";
210			clocks = <&gclk 35>, <&mclk 0x20 1>;
211			clock-names = "GCLK", "MCLK";
212		};
213
214		sercom6: sercom@43000800 {
215			compatible = "atmel,sam0-sercom";
216			reg = <0x43000800 0x40>;
217			interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
218			status = "disabled";
219			clocks = <&gclk 36>, <&mclk 0x20 2>;
220			clock-names = "GCLK", "MCLK";
221		};
222
223		sercom7: sercom@43000c00 {
224			compatible = "atmel,sam0-sercom";
225			reg = <0x43000C00 0x40>;
226			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
227			status = "disabled";
228			clocks = <&gclk 37>, <&mclk 0x20 3>;
229			clock-names = "GCLK", "MCLK";
230		};
231
232		pinctrl: pinctrl@41008000 {
233			compatible = "atmel,sam0-pinctrl";
234			#address-cells = <1>;
235			#size-cells = <1>;
236			ranges = <0x41008000 0x41008000 0x200>;
237
238			porta: gpio@41008000 {
239				compatible = "atmel,sam0-gpio";
240				reg = <0x41008000 0x80>;
241				gpio-controller;
242				#gpio-cells = <2>;
243				#atmel,pin-cells = <2>;
244			};
245
246			portb: gpio@41008080 {
247				compatible = "atmel,sam0-gpio";
248				reg = <0x41008080 0x80>;
249				gpio-controller;
250				#gpio-cells = <2>;
251				#atmel,pin-cells = <2>;
252			};
253
254			portc: gpio@41008100 {
255				compatible = "atmel,sam0-gpio";
256				reg = <0x41008100 0x80>;
257				gpio-controller;
258				#gpio-cells = <2>;
259				#atmel,pin-cells = <2>;
260			};
261
262			portd: gpio@41008180 {
263				compatible = "atmel,sam0-gpio";
264				reg = <0x41008180 0x80>;
265				gpio-controller;
266				#gpio-cells = <2>;
267				#atmel,pin-cells = <2>;
268			};
269		};
270
271		usb0: usb@41000000 {
272			compatible = "atmel,sam0-usb";
273			status = "disabled";
274			reg = <0x41000000 0x1000>;
275			interrupts = <80 0>, <81 0>, <82 0>, <83 0>;
276			num-bidir-endpoints = <8>;
277		};
278
279		trng: random@42002800 {
280			compatible = "atmel,sam-trng";
281			reg = <0x42002800 0x1e>;
282			interrupts = <131 0>;
283		};
284
285		rtc: rtc@40002400 {
286			compatible = "atmel,sam0-rtc";
287			reg = <0x40002400 0x1C>;
288			interrupts = <11 0>;
289			clock-generator = <0>;
290			status = "disabled";
291		};
292
293		adc0: adc@43001c00 {
294			compatible = "atmel,sam0-adc";
295			reg = <0x43001C00 0x4A>;
296			interrupts = <118 0>, <119 0>;
297			interrupt-names = "overrun", "resrdy";
298
299			/*
300			 * 16 MHz max, source clock must not exceed 100 MHz.
301			 *	- table 54-8, section 54.6, page 2020
302			 *	- table 54-24, section 54.10.4, page 2031
303			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
304			 */
305			gclk = <2>;
306			prescaler = <4>;
307			#io-channel-cells = <1>;
308			clocks = <&gclk 40>, <&mclk 0x20 7>;
309			clock-names = "GCLK", "MCLK";
310			calib-offset = <0>;
311		};
312
313		adc1: adc@43002000 {
314			compatible = "atmel,sam0-adc";
315			reg = <0x43002000 0x4A>;
316			interrupts = <120 0>, <121 0>;
317			interrupt-names = "overrun", "resrdy";
318
319			/*
320			 * 16 MHz max, source clock must not exceed 100 MHz.
321			 *	- table 54-8, section 54.6, page 2020
322			 *	- table 54-24, section 54.10.4, page 2031
323			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
324			 */
325			gclk = <2>;
326			prescaler = <4>;
327			#io-channel-cells = <1>;
328			clocks = <&gclk 41>, <&mclk 0x20 8>;
329			clock-names = "GCLK", "MCLK";
330			calib-offset = <14>;
331		};
332
333		tc0: tc@40003800 {
334			compatible = "atmel,sam0-tc32";
335			reg = <0x40003800 0x34>;
336			interrupts = <107 0>;
337			clocks = <&gclk 9>, <&mclk 0x14 14>;
338			clock-names = "GCLK", "MCLK";
339		};
340
341		tc2: tc@4101a000 {
342			compatible = "atmel,sam0-tc32";
343			reg = <0x4101A000 0x34>;
344			interrupts = <109 0>;
345			clocks = <&gclk 26>, <&mclk 0x18 13>;
346			clock-names = "GCLK", "MCLK";
347		};
348
349		tc4: tc@42001400 {
350			compatible = "atmel,sam0-tc32";
351			reg = <0x42001400 0x34>;
352			interrupts = <111 0>;
353			clocks = <&gclk 30>, <&mclk 0x1c 5>;
354			clock-names = "GCLK", "MCLK";
355		};
356
357		tc6: tc@43001400 {
358			compatible = "atmel,sam0-tc32";
359			reg = <0x43001400 0x34>;
360			interrupts = <113 0>;
361			clocks = <&gclk 39>, <&mclk 0x20 5>;
362			clock-names = "GCLK", "MCLK";
363		};
364
365		tcc0: tcc@41016000 {
366			compatible = "atmel,sam0-tcc";
367			reg = <0x41016000 0x2000>;
368			interrupts = <85 0>, <86 0>, <87 0>, <88 0>, <89 0>,
369				     <90 0>, <91 0>;
370			clocks = <&gclk 25>, <&mclk 0x18 11>;
371			clock-names = "GCLK", "MCLK";
372			channels = <6>;
373			counter-size = <24>;
374		};
375
376		tcc1: tcc@41018000 {
377			compatible = "atmel,sam0-tcc";
378			reg = <0x41018000 0x2000>;
379			interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>;
380			clocks = <&gclk 25>, <&mclk 0x18 12>;
381			clock-names = "GCLK", "MCLK";
382			channels = <4>;
383			counter-size = <24>;
384		};
385
386		tcc2: tcc@42000c00 {
387			compatible = "atmel,sam0-tcc";
388			reg = <0x42000c00 0x400>;
389			interrupts = <97 0>, <98 0>, <99 0>, <100 0>;
390			clocks = <&gclk 29>, <&mclk 0x1c 3>;
391			clock-names = "GCLK", "MCLK";
392			channels = <3>;
393			counter-size = <16>;
394		};
395
396		tcc3: tcc@42001000 {
397			compatible = "atmel,sam0-tcc";
398			reg = <0x42001000 0x400>;
399			interrupts = <101 0>, <102 0>, <103 0>;
400			clocks = <&gclk 29>, <&mclk 0x1c 4>;
401			clock-names = "GCLK", "MCLK";
402			channels = <2>;
403			counter-size = <16>;
404		};
405
406		tcc4: tcc@43001000 {
407			compatible = "atmel,sam0-tcc";
408			reg = <0x43001000 0x400>;
409			interrupts = <104 0>, <105 0>, <106 0>;
410			clocks = <&gclk 38>, <&mclk 0x20 4>;
411			clock-names = "GCLK", "MCLK";
412			channels = <2>;
413			counter-size = <16>;
414		};
415	};
416};
417
418&nvic {
419	arm,num-irq-priority-bits = <3>;
420};
421