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/Zephyr-latest/include/zephyr/
Dirq_multilevel.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Public interface for multi-level interrupts
26 /* Zephyr multilevel-encoded IRQ */
31 /* First level interrupt bits */
33 /* Second level interrupt bits */
35 /* Third level interrupt bits */
39 /* Third level IRQ's interrupt controller */
41 /* IRQ of the third level interrupt aggregator */
45 /* Second level IRQ's interrupt controller */
47 /* IRQ of the second level interrupt aggregator */
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Dsw_isr_table.h4 * SPDX-License-Identifier: Apache-2.0
9 * @brief Software-managed ISR table
11 * Data types for a software-managed ISR table, with a parameter per-ISR.
36 * loaded arg -> r0, isr -> r3 in _isr_wrapper with one ldmia instruction,
37 * on ARM Cortex-M (Thumb2).
51 unsigned int level; member
60 /* Mapping between aggregator level to order */
61 #define Z_STR_L2 2ND
64 * @brief Get the Software ISR table offset Kconfig for the given aggregator level
66 * @param l Aggregator level, must be 2 or 3
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/Zephyr-latest/include/zephyr/devicetree/
Dinterrupt_controller.h4 * SPDX-License-Identifier: Apache-2.0
23 * @defgroup devicetree-interrupt_controller Devicetree Interrupt Controller API
29 * @brief Get the aggregator level of an interrupt controller
31 * @note Aggregator level is equivalent to IRQ_LEVEL + 1 (a 2nd level aggregator has Zephyr level 1
36 * @return Level of the interrupt controller
41 * @brief Get the aggregator level of a `DT_DRV_COMPAT` interrupt controller
43 * @note Aggregator level is equivalent to IRQ_LEVEL + 1 (a 2nd level aggregator has Zephyr level 1
48 * @return Level of the interrupt controller
/Zephyr-latest/drivers/interrupt_controller/
DKconfig.multilevel5 # SPDX-License-Identifier: Apache-2.0
8 bool "Multi-level interrupt support"
13 levels are used, a second level interrupt aggregator would combine
14 all interrupts routed to it into one IRQ line in the first level
15 interrupt controller. If three levels are used, a third level
17 second level. The number of interrupt levels is usually determined
23 int "Total number of first level interrupt bits"
38 config 2ND_LEVEL_INTERRUPTS
39 bool "Second-level interrupt support"
41 Second level interrupts are used to increase the number of
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DKconfig.dw2 # SPDX-License-Identifier: Apache-2.0
18 Designware Interrupt Controller can be used as a 2nd level interrupt
20 that is then routed to the 1st level interrupt controller.
/Zephyr-latest/dts/bindings/interrupt-controller/
Dsnps,archs-idu-intc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 ARC-HS Interrupt Distribution Unit 2nd-level interrupt controller. Can be
9 compatible: "snps,archs-idu-intc"
11 include: [interrupt-controller.yaml, base.yaml]
13 interrupt-cells:
14 - irq
15 - priority
/Zephyr-latest/scripts/build/
Dgen_isr_tables.py7 # SPDX-License-Identifier: Apache-2.0
26 Note - this function requires config global variable to be initialized.
57 return (1 << bits) - 1
78 # levels of interrupts in a multi-level interrupt system.
79 # 0x000000FF - represents the 1st level (i.e. the interrupts
81 # 0x0000FF00 - represents the 2nd level (i.e. the interrupts funnel
82 # into 1 line which then goes into the 1st level)
83 # 0x00FF0000 - represents the 3rd level (i.e. the interrupts funnel
84 # into 1 line which then goes into the 2nd level)
97 self.__int_bits[2] = self.get_sym("CONFIG_3RD_LEVEL_INTERRUPT_BITS")
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/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/include/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
22 * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
/Zephyr-latest/soc/nxp/imx/imx8x/adsp/include/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
22 * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
/Zephyr-latest/soc/nxp/imx/imx8/adsp/include/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
22 * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
/Zephyr-latest/soc/nxp/imx/imx8m/adsp/include/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
22 * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
/Zephyr-latest/soc/nxp/imxrt/imxrt5xx/f1/include/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
22 * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
/Zephyr-latest/tests/drivers/interrupt_controller/multi_level_backend/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
24 /* Device pointer to level 2 intc 1 */
26 /* Device pointer to level 2 intc 2 */
28 /* Device pointer to level 3 intc 3*/
30 /* Device pointer to level 3 intc 4 */
36 /* Local IRQ of level 2 intc 1 */
38 /* Local IRQ of level 2 intc 2 */
40 /* Local IRQ of level 3 intc 3 */
42 /* Local IRQ of level 3 intc 4 */
48 /* Zephyr IRQ of level 2 intc 1 */
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/Zephyr-latest/dts/bindings/dma/
Dst,stm32-bdma.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The STM32 BDMA is a general-purpose direct memory access controller
11 described in the dma.txt file, using a four-cell specifier for each
13 1. channel: the bdma stream from 0 to <bdma-requests>
14 2. slot: bdma request
15 3. channel-config: A 32bit mask specifying the BDMA channel configuration
17 -bit 6-7 : Direction (see dma.h)
22 -bit 9 : Peripheral Increment Address
25 -bit 10 : Memory Increment Address
28 -bit 11-12 : Peripheral data size
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/Zephyr-latest/soc/intel/intel_adsp/cavs/
Dirq.c2 * SPDX-License-Identifier: Apache-2.0
14 #include <cavs-idc.h>
37 case DT_IRQN(CAVS_INTC_NODE(2)): in z_soc_irq_enable()
38 dev_cavs = DEVICE_DT_GET(CAVS_INTC_NODE(2)); in z_soc_irq_enable()
75 case DT_IRQN(CAVS_INTC_NODE(2)): in z_soc_irq_disable()
76 dev_cavs = DEVICE_DT_GET(CAVS_INTC_NODE(2)); in z_soc_irq_disable()
116 case DT_IRQN(CAVS_INTC_NODE(2)): in z_soc_irq_is_enabled()
117 dev_cavs = DEVICE_DT_GET(CAVS_INTC_NODE(2)); in z_soc_irq_is_enabled()
130 ret = -ENODEV; in z_soc_irq_is_enabled()
153 /* extract 2nd level interrupt number */ in z_soc_irq_connect_dynamic()
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/Zephyr-latest/samples/subsys/smf/hsm_psicc2/src/
Dhsm_psicc2_console_cmds.c6 * Practical UML Statecharts in C/C++, 2nd Edition by Miro Samek
7 * https://www.state-machine.com/psicc2
10 * SPDX-License-Identifier: Apache-2.0
54 return -1; in cmd_hsm_psicc2_event()
80 /* Creating subcommands (level 1 command) array for command "demo". */
83 cmd_hsm_psicc2_event, 2, 0),
89 /* Creating root (level 0) command "demo" */
/Zephyr-latest/samples/boards/nordic/mesh/onoff_level_lighting_vnd_app/src/mesh/
Dstate_binding.c1 /* Bluetooth: Mesh Generic OnOff, Generic Level, Lighting & Vendor Models
5 * SPDX-License-Identifier: Apache-2.0
44 if (light > 0 && light < ctl->light->range_min) { in constrain_lightness()
45 light = ctl->light->range_min; in constrain_lightness()
46 } else if (light > ctl->light->range_max) { in constrain_lightness()
47 light = ctl->light->range_max; in constrain_lightness()
56 if (ctl->light->target > 0 && in constrain_target_lightness2()
57 ctl->light->target < ctl->light->range_min) { in constrain_target_lightness2()
58 if (ctl->light->delta < 0) { in constrain_target_lightness2()
59 ctl->light->target = 0U; in constrain_target_lightness2()
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/Zephyr-latest/drivers/pwm/
Dpwm_mcux_ftm.c3 * Copyright (c) 2020-2021 Vestas Wind Systems A/S
5 * SPDX-License-Identifier: Apache-2.0
23 #define MAX_CHANNELS ARRAY_SIZE(FTM0->CONTROLS)
26 #define MAX_CAPTURE_PAIRS (MAX_CHANNELS / 2U)
27 #define PAIR_1ST_CH(pair) (pair * 2U)
68 const struct mcux_ftm_config *config = dev->config; in mcux_ftm_set_cycles()
69 struct mcux_ftm_data *data = dev->data; in mcux_ftm_set_cycles()
72 uint32_t pair = channel / 2U; in mcux_ftm_set_cycles()
77 LOG_ERR("Channel can not be set to inactive level"); in mcux_ftm_set_cycles()
78 return -ENOTSUP; in mcux_ftm_set_cycles()
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/Zephyr-latest/arch/xtensa/core/
Dcrt1.S3 * SPDX-License-Identifier: Apache-2.0
34 # define ARG2 a3 /* 2nd outgoing call argument */
42 # define ARG2 a7 /* 2nd outgoing call argument */
53 * _start is typically NOT at the beginning of the text segment --
58 * - low (level-one) and medium priority interrupts are disabled
60 * - C calling context not initialized:
61 * - PS not initialized
62 * - SP not initialized
63 * - the following are initialized:
64 * - LITBASE, cache attributes, WindowBase, WindowStart,
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/Zephyr-latest/subsys/net/ip/
DKconfig.ipv64 # SPDX-License-Identifier: Apache-2.0
18 default 2 if NET_LOOPBACK
28 default 2
37 default 2
113 default 2
116 Incoming fragments are stored in per-packet queue before being
160 The value depends on your network needs. ND should normally
194 By default the legacy format using EUI-64 (MAC address) specified in
202 bool "Generate IID using EUI-64"
204 Generate IID from modified EUI-64 a.k.a MAC address. This is the
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/Zephyr-latest/scripts/native_simulator/common/src/
Dnsi_hw_scheduler.c5 * SPDX-License-Identifier: Apache-2.0
55 * Therefore we set SA_RESETHAND: This way, the 2nd time the signal is received
148 * as NSI_TASKS of HW_INIT level.
152 number_of_events = __nsi_hw_events_end - __nsi_hw_events_start; in nsi_hws_init()
/Zephyr-latest/arch/xtensa/include/
Dxtensa_asm2_s.h4 * SPDX-License-Identifier: Apache-2.0
27 * A0-A15) to their ABI-defined spill regions on the stack.
35 * and repeats until all but the A0-A3 registers of the original frame
39 * - Vastly smaller code size
41 * - More easily maintained if changes are needed to window over/underflow
44 * - Requires no scratch registers to do its work, so can be used safely in any
47 * - If the WOE bit is not enabled (for example, in code written for
50 * - In memory protection situations, this relies on the existing
57 * - Hilariously it's ACTUALLY FASTER than the HAL routine. And not
59 * file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
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/Zephyr-latest/arch/arc/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
32 select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || (ARC_MPU && ARC_MPU_VER !=2)
38 v2 ISA for the ARC-HS & ARC-EM cores
66 If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
67 floating-point extension
73 If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
74 floating-point and double assist instructions
135 - LPcc instruction
136 - LP_COUNT core reg
137 - LP_START, LP_END aux regs
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/Zephyr-latest/drivers/video/
Dov2640.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/drivers/video-controls.h>
200 { COM19, 0x00 }, /* Zoom control 2 LSBs */
379 /* {HSIZE[11], HSIZE[2:0], VSIZE[2:0]} */
384 { HSIZE, ((UXGA_HSIZE>>2)&0xFF) }, /* H_SIZE[7:0] real/4 */
385 { VSIZE, ((UXGA_VSIZE>>2)&0xFF) }, /* V_SIZE[7:0] real/4 */
407 { 0x00, 0x04, 0x09, 0x00, 0x00 }, /* -2 */
408 { 0x00, 0x04, 0x09, 0x10, 0x00 }, /* -1 */
411 { 0x00, 0x04, 0x09, 0x40, 0x00 }, /* +2 */
417 { 0x00, 0x04, 0x07, 0x20, 0x18, 0x34, 0x06 }, /* -2 */
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/Zephyr-latest/arch/xtensa/core/startup/
Dreset_vector.S3 * SPDX-License-Identifier: Apache-2.0
10 #include <xtensa/xtensa-xer.h>
11 #include <xtensa/xdm-regs.h>
14 #include <xtensa/xtruntime-core-state.h>
42 .size __start, . - __start
57 #warning "Xtensa TX reset vector not at start of iram0, irom0, or uram0 -- ROMing LSPs may not work"
76 * Even if the processor supports the non-PC-relative L32R option,
77 * it will always start up in PC-relative mode. We take advantage of
78 * this, and use PC-relative mode at least until we're sure the .lit4
81 .begin no-absolute-literals
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