Lines Matching +full:2 +full:nd +full:- +full:level
4 # SPDX-License-Identifier: Apache-2.0
32 select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || (ARC_MPU && ARC_MPU_VER !=2)
38 v2 ISA for the ARC-HS & ARC-EM cores
66 If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision
67 floating-point extension
73 If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision
74 floating-point and double assist instructions
135 - LPcc instruction
136 - LP_COUNT core reg
137 - LP_START, LP_END aux regs
144 Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1.
153 Interrupts available will be 0 to NUM_IRQS-1.
164 range 1 2
165 default 2
168 bank. If fast interrupts are supported (FIRQ), the 2nd
173 NOTE: it's required to have more than one interrupt priority level
174 to use second register bank - otherwise all interrupts will use
191 interrupt priority level (so all interrupts are FIRQ). Such
235 select MPU_STACK_GUARD if (!ARC_STACK_CHECKING && ARC_MPU && ARC_MPU_VER !=2)
239 - The ARC stack checking, or
240 - the MPU-based stack guard
245 prioritized over the MPU-based stack guard.
252 ARC EM cores w/o secure shield 2+2 mode support might be configured
262 RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization
289 Depending on the configuration, CPU can contain accumulator reg-pair
386 bool "Make early stage SoC-specific initialization"
388 Call SoC per-core setup code on early stage initialization