Lines Matching +full:2 +full:nd +full:- +full:level

5 # SPDX-License-Identifier: Apache-2.0
8 	bool "Multi-level interrupt support"
13 	  levels are used, a second level interrupt aggregator would combine
14 	  all interrupts routed to it into one IRQ line in the first level
15 	  interrupt controller. If three levels are used, a third level
17 	  second level. The number of interrupt levels is usually determined
23 	int "Total number of first level interrupt bits"
38 config 2ND_LEVEL_INTERRUPTS
39 	bool "Second-level interrupt support"
41 	  Second level interrupts are used to increase the number of
44 config 2ND_LVL_ISR_TBL_OFFSET
45 	int "Offset in _sw_isr_table for level 2 interrupts"
47 	depends on 2ND_LEVEL_INTERRUPTS
50 	  where storage for 2nd level interrupt ISRs begins. This is
51 	  typically allocated after ISRs for level 1 interrupts.
54 	int "Total number of second level interrupt aggregators"
57 	depends on 2ND_LEVEL_INTERRUPTS
59 	  The number of level 2 interrupt aggregators to support. Each
60 	  aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 2
63 config 2ND_LEVEL_INTERRUPT_BITS
64 	int "Total number of second level interrupt bits"
71 prev-level-num = 1
72 cur-level-num = 2
73 cur-level = 2ND
78 aggregator = 2
92 	bool "Third-level interrupt support"
93 	depends on 2ND_LEVEL_INTERRUPTS
95 	  Third level interrupts are used to increase the number of
99 	int "Total number of third level interrupt aggregators"
104 	  The number of level 3 interrupt aggregators to support. Each
105 	  aggregator can manage at most MAX_IRQ_PER_AGGREGATOR level 3
109 	int "Offset in _sw_isr_table for level 3 interrupts"
114 	  where storage for 3rd level interrupt ISRs begins. This is
115 	  typically allocated after ISRs for level 2 interrupts.
118 	int "Total number of third level interrupt bits"
125 prev-level-num = 2
126 cur-level-num = 3
127 cur-level = 3RD
132 aggregator = 2