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/Zephyr-latest/drivers/serial/
Duart_rzt2m.h4 * SPDX-License-Identifier: Apache-2.0
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
/Zephyr-latest/drivers/spi/
Dspi_pw.h1 /* spi_pw.h - Penwell SPI driver definitions */
6 * SPDX-License-Identifier: Apache-2.0
41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
48 #define PW_SPI_CTRLR0_EDSS_MASK (~(0x1 << 20))
65 #define PW_SPI_BR_MAX_FRQ 20000000 /* 20 MHz */
71 #define PW_SPI_CTRL1_RIE_BIT BIT(0)
[all …]
Dspi_andes_atcspi200.h4 * SPDX-License-Identifier: Apache-2.0
44 #define TFMAT_CPHA_MSK BIT(0)
45 #define TFMAT_CPOL_MSK BIT(1)
46 #define TFMAT_SLVMODE_MSK BIT(2)
47 #define TFMAT_LSB_MSK BIT(3)
48 #define TFMAT_DATA_MERGE_MSK BIT(7)
57 #define TCTRL_WR_TCNT_MSK GENMASK(20, 12)
66 #define IEN_RX_FIFO_MSK BIT(2)
67 #define IEN_TX_FIFO_MSK BIT(3)
68 #define IEN_END_MSK BIT(4)
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/memory-attr/
Dmemory-attr.h4 * SPDX-License-Identifier: Apache-2.0
20 #define DT_MEM_CACHEABLE BIT(0) /* cacheable */
21 #define DT_MEM_NON_VOLATILE BIT(1) /* non-volatile */
22 #define DT_MEM_OOO BIT(2) /* out-of-order */
23 #define DT_MEM_DMA BIT(3) /* DMA-able */
24 #define DT_MEM_UNKNOWN BIT(15) /* must be last */
36 #define DT_MEM_SW_ATTR_UNKNOWN BIT(19)
44 * See for example `include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h`
46 #define DT_MEM_ARCH_ATTR_MASK GENMASK(31, 20)
48 #define DT_MEM_ARCH_ATTR_SHIFT (20)
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/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
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/Zephyr-latest/arch/x86/include/
Dkernel_arch_data.h3 * SPDX-License-Identifier: Apache-2.0
10 * Exception/interrupt vector definitions: vectors 20 to 31 are reserved
34 #define IV_VIRT_EXCEPTION 20
41 * EFLAGS/RFLAGS definitions. (RFLAGS is just zero-extended EFLAGS.)
44 #define EFLAGS_IF BIT(9) /* interrupts enabled */
45 #define EFLAGS_DF BIT(10) /* Direction flag */
53 #define CR0_PG BIT(31) /* enable paging */
54 #define CR0_WP BIT(16) /* honor W bit even when supervisor */
56 #define CR4_PSE BIT(4) /* Page size extension (4MB pages) */
57 #define CR4_PAE BIT(5) /* enable PAE */
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
48 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
47 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
55 #define SSCR0_EFRDC BIT(27)
[all …]
/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
105 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
[all …]
/Zephyr-latest/include/zephyr/arch/arm64/
Dcpu.h4 * SPDX-License-Identifier: Apache-2.0
13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
[all …]
/Zephyr-latest/drivers/pcie/endpoint/
Dpcie_ep_iproc.h4 * SPDX-License-Identifier: Apache-2.0
17 #define PCIE_LINKWIDTH_SHIFT 20
34 #define MSIX_FUNC_MASK BIT(30)
45 #define MSIX_TABLE_SIZE 16 /* we support 16 MSI-X */
50 #define MSIX_VECTOR_MASK BIT(0)
59 #define PAXB_OARR_VALID BIT(0)
63 #define SNOOP_VALID_INTR BIT(3)
64 #define SNOOP_ADDR1_EN BIT(31)
74 #define AXI_FILTER_0_ENABLE (BIT(30) | BIT(2) | \
75 BIT(1) | BIT(0))
[all …]
/Zephyr-latest/drivers/edac/
Dibecc.h4 * SPDX-License-Identifier: Apache-2.0
35 #define NMI_STS_SRC_SERR BIT(7)
43 #define NMI_STS_SERR_EN BIT(2)
48 * In-Band Error Correction Code (IBECC) protects data at a cache line
51 * - CMI (Converged Memory Interface) Address
52 * - Syndrome
53 * - Error Type (Correctable, Uncorrectable)
60 /* Top of Upper Usable DRAM, offset 0xa8, 64 bit */
62 #define TOUUD_MASK GENMASK64(38, 20)
64 /* Top of Low Usable DRAM, offset 0xbc, 32 bit */
[all …]
/Zephyr-latest/drivers/dma/
Ddma_dw_common.h4 * SPDX-License-Identifier: Apache-2.0
18 (((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL) << (b_lo))
21 (((x) & ((1ULL << ((b_hi) - (b_lo) + 1ULL)) - 1ULL)) << (b_lo))
84 #define DW_CHAN_WRITE_EN_ALL MASK(2 * DW_MAX_CHAN - 1, DW_MAX_CHAN)
85 #define DW_CHAN_WRITE_EN(chan) BIT((chan) + DW_MAX_CHAN)
86 #define DW_CHAN_ALL MASK(DW_MAX_CHAN - 1, 0)
87 #define DW_CHAN(chan) BIT(chan)
94 #define DW_CFGL_RELOAD_DST BIT(31)
95 #define DW_CFGL_RELOAD_SRC BIT(30)
96 #define DW_CFGL_DRAIN BIT(10) /* For Intel GPDMA variant only */
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace15_mtpm/
Ddmic_regs_ace1x.h1 /* SPDX-License-Identifier: Apache-2.0 */
20 #define DMICLCAP_CLTSS BIT(5)
23 #define DMICLCAP_LSS BIT(6)
26 #define DMICLCAP_SCMS BIT(7)
29 #define DMICLCAP_MLCS BIT(8)
32 #define DMICLCAP_PW BIT(26)
35 #define DMICLCAP_OSEL BIT(27)
45 #define DMICIPPTR_PTR GENMASK(20, 0)
58 #define DMICSYNC_SYNCPU BIT(15)
61 #define DMICSYNC_CMDSYNC BIT(16)
[all …]
/Zephyr-latest/soc/neorv32/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
21 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
22 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
23 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
24 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
25 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
26 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
27 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
28 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
29 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace30/
Ddmic_regs_ace3x.h3 * SPDX-License-Identifier: Apache-2.0
16 #define DMICSYNC_SYNCPU BIT(20)
19 #define DMICSYNC_SYNCGO BIT(23)
22 #define DMICSYNC_CMDSYNC BIT(24)
31 #define DMICLCTL_OFLEN BIT(4)
34 #define DMICLCTL_INTEN BIT(5)
37 #define DMICLCTL_SPA BIT(16)
40 #define DMICLCTL_CPA BIT(23)
43 #define DMICLCTL_INTSTS BIT(31)
49 #define DMICLVSCTL_FCG BIT(26)
[all …]
/Zephyr-latest/drivers/sensor/st/lis3mdl/
Dlis3mdl.h4 * SPDX-License-Identifier: Apache-2.0
21 #define LIS3MDL_TEMP_EN_MASK BIT(7)
23 #define LIS3MDL_OM_MASK (BIT(6) | BIT(5))
25 #define LIS3MDL_MAG_DO_MASK (BIT(4) | BIT(3) | BIT(2))
27 #define LIS3MDL_FAST_ODR_MASK BIT(1)
29 #define LIS3MDL_ST_MASK BIT(0)
38 #define LIS3MDL_FS_MASK (BIT(6) | BIT(5))
40 #define LIS3MDL_REBOOT_MASK BIT(3)
42 #define LIS3MDL_SOFT_RST_MASK BIT(2)
45 #define LIS3MDL_FS_IDX ((CONFIG_LIS3MDL_FS / 4) - 1)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
D_soc_inthandlers.h3 * SPDX-License-Identifier: Apache-2.0
12 * order (low bits first) and will return a mask of that bit that can
17 #include <xtensa/config/core-isa.h>
22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
49 #define SCARH_ENABLE BIT(3)
50 #define SCARH_ADDR_BIT19 BIT(7)
53 * SCAR registers contain 20-bit addresses in three registers, with one set
61 /* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
76 return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0; in is_block_aligned()
83 return -EFAULT; /* Not in RAM */ in it8xxx2_configure_ilm_block()
[all …]
/Zephyr-latest/soc/intel/intel_adsp/ace/include/ace20_lnl/
Ddmic_regs_ace2x.h1 /* SPDX-License-Identifier: Apache-2.0 */
18 #define DMICSYNC_SYNCPU BIT(20)
21 #define DMICSYNC_SYNCGO BIT(23)
24 #define DMICSYNC_CMDSYNC BIT(24)
34 #define DMICLCTL_OFLEN BIT(4)
37 #define DMICLCTL_INTEN BIT(5)
40 #define DMICLCTL_SPA BIT(16)
43 #define DMICLCTL_CPA BIT(23)
46 #define DMICLCTL_INTSTS BIT(31)
53 #define DMICLVSCTL_FCG BIT(26)
[all …]

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