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/Zephyr-latest/subsys/net/l2/ethernet/lldp/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
15 module-dep = NET_LOG
16 module-str = Log level for LLDP
17 module-help = Enables core LLDP code to output debug messages.
29 (non-fast mode) transmission periods. For further information
62 Subtype 2 = Interface alias
74 hex "Chassis ID MAC Address Byte 0"
78 Byte 0 of the MAC address.
81 hex "Chassis ID MAC Address Byte 1"
85 Byte 1 of the MAC address.
[all …]
/Zephyr-latest/drivers/flash/
Dspi_nor.h2 * Copyright (c) 2018 Savoir-Faire Linux.
4 * SPDX-License-Identifier: Apache-2.0
21 #define SPI_NOR_CMD_WRSR2 0x31 /* Write status register 2 */
22 #define SPI_NOR_CMD_RDSR2 0x35 /* Read status register 2 */
27 #define SPI_NOR_CMD_DREAD 0x3B /* Read data (1-1-2) */
28 #define SPI_NOR_CMD_2READ 0xBB /* Read data (1-2-2) */
29 #define SPI_NOR_CMD_QREAD 0x6B /* Read data (1-1-4) */
30 #define SPI_NOR_CMD_4READ 0xEB /* Read data (1-4-4) */
34 #define SPI_NOR_CMD_PP_1_1_2 0xA2 /* Dual Page program (1-1-2) */
35 #define SPI_NOR_CMD_PP_1_1_4 0x32 /* Quad Page program (1-1-4) */
[all …]
DKconfig.npcx_fiu4 # SPDX-License-Identifier: Apache-2.0
36 This option enables the QSPI NOR Flash features such as Quad-Enable,
37 4-byte address support and so on during driver initialization. Disable
47 bool "Direct Read Access version 2 support"
53 bool "4 byte address support in Direct Read Access mode"
57 Selected if NPCX series supports 4 byte address mode in Direct Read
61 bool "4 byte address support in Direct Read Access mode"
/Zephyr-latest/drivers/sensor/st/stmemsc/
Dstmemsc_spi.c5 * SPDX-License-Identifier: Apache-2.0
7 * zephyrproject-rtos/modules/hal/st/sensor/stmemsc/
14 /* Enable address auto-increment on some stmemsc sensors */
23 uint8_t buffer_tx[2] = { reg_addr | SPI_READ, 0 }; in stmemsc_spi_read()
25 /* write 1 byte with reg addr (msb at 1) + 1 dummy byte */ in stmemsc_spi_read()
26 const struct spi_buf tx_buf = { .buf = buffer_tx, .len = 2, }; in stmemsc_spi_read()
30 * transaction #1: dummy read to skip first byte in stmemsc_spi_read()
31 * transaction #2: read "len" byte of data in stmemsc_spi_read()
33 const struct spi_buf rx_buf[2] = { in stmemsc_spi_read()
37 const struct spi_buf_set rx = { .buffers = rx_buf, .count = 2 }; in stmemsc_spi_read()
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/Zephyr-latest/subsys/modbus/
Dmodbus_server.c4 * SPDX-License-Identifier: Apache-2.0
13 * Copyright 2003-2020 Silicon Laboratories Inc. www.silabs.com
15 * SPDX-License-Identifier: APACHE-2.0
19 * Version 2.0 available at www.apache.org/licenses/LICENSE-2.0.
37 ctx->mbs_msg_ctr = 0; in modbus_reset_stats()
38 ctx->mbs_crc_err_ctr = 0; in modbus_reset_stats()
39 ctx->mbs_except_ctr = 0; in modbus_reset_stats()
40 ctx->mbs_server_msg_ctr = 0; in modbus_reset_stats()
41 ctx->mbs_noresp_ctr = 0; in modbus_reset_stats()
46 ctx->mbs_msg_ctr++; in update_msg_ctr()
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/Zephyr-latest/include/zephyr/drivers/i3c/
Dccc.h5 * SPDX-License-Identifier: Apache-2.0
68 * Enter Activity State 2
72 #define I3C_CCC_ENTAS2(broadcast) I3C_CCC_ENTAS(2, broadcast)
117 /** Enter HDR Mode (HDR-DDR) (Broadcast) */
120 /** Enter HDR Mode 0 (HDR-DDR) (Broadcast) */
123 /** Enter HDR Mode 1 (HDR-TSP) (Broadcast) */
126 /** Enter HDR Mode 2 (HDR-TSL) (Broadcast) */
129 /** Enter HDR Mode 3 (HDR-BT) (Broadcast) */
171 /** Multi-Lane Data Transfer Control (Broadcast) */
243 * - For Write CCC, pointer to the byte array of data
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/Zephyr-latest/arch/arm64/core/
Dearly_mem_funcs.S4 * SPDX-License-Identifier: Apache-2.0
25 /* is dst pointer 8-bytes aligned? */
27 b.ne 2f
31 b.lo 2f
33 /* spread the byte value across whole 64 bits */
44 2: /* at least one byte to set? */
47 3: /* one byte at a time */
58 /* are dst and src pointers 8-bytes aligned? */
61 b.ne 2f
65 b.lo 2f
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/Zephyr-latest/samples/drivers/lcd_cyclonev_socdk/src/
Dcommands.h2 * SPDX-License-Identifier: Apache-2.0
6 * Reference: https://datasheetspdf.com/pdf-file/746090/Newhaven/NHD-0216K3Z-NSW-BBW/1
12 #define SET_CURSOR 0x45 /*1 byte param in range (0x00 - 0x4F) 2x16 display */
22 #define SET_CONTRAST 0x52 /* 1 byte param in range (1 - 50) 40 default */
23 #define SET_BACKLIGHT 0x53 /* 1 byte param in range (1 - 8) 1 default */
25 #define LD_CUSTOM_CHAR 0x54 /* 9 byte param 1st param: 1-byte */
30 * [addr] 1 byte Custom character address, 0 – 7
34 * Bit 7 6 5 4 3 2 1 0 Hex
47 #define CHGE_RS232_BAUD 0x61 /* 1 byte param in range (1 - 8) */
53 * 2 1200
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/Zephyr-latest/drivers/smbus/
Dintel_pch_smbus.h7 * PCH provides SMBus 2.0 - compliant Host Controller.
9 * SPDX-License-Identifier: Apache-2.0
17 /* Host Configuration (HCFG) - Offset 40h, 8 bits */
27 #define PCH_SMBUS_HSTS_DEV_ERROR BIT(2) /* Device Error */
32 #define PCH_SMBUS_HSTS_BYTE_DONE BIT(7) /* Byte Done */
42 #define PCH_SMBUS_HCTL_CMD GENMASK(4, 2) /* Command */
44 #define PCH_SMBUS_HCTL_CMD_QUICK (0 << 2) /* Quick cmd*/
45 #define PCH_SMBUS_HCTL_CMD_BYTE (1 << 2) /* Byte cmd */
46 #define PCH_SMBUS_HCTL_CMD_BYTE_DATA (2 << 2) /* Byte Data cmd */
47 #define PCH_SMBUS_HCTL_CMD_WORD_DATA (3 << 2) /* Word Data cmd */
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/Zephyr-latest/drivers/mipi_dsi/
DKconfig.mcux1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
5 bool "NXP MCUX MIPI-DSI Host Controller"
12 bool "NXP MCUX MIPI-DSI 2L Controller"
16 NXP MIPI DSI 2L controller driver
30 bool "Swap 16 byte color"
32 Swap 16 byte color data from little to big endian format. When
34 format, which will then be byte swapped.
/Zephyr-latest/include/zephyr/drivers/
Dsmbus.h4 * SPDX-License-Identifier: Apache-2.0
49 * 0 1 2 3 4 5 6 7 8 9 0
50 * +-+-+-+-+-+-+-+-+-+-+-+
52 * +-+-+-+-+-+-+-+-+-+-+-+
58 * SMBus Byte protocol can send or receive one byte of data.
61 * Byte Write
63 * 0 1 2
64 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0
65 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
67 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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/Zephyr-latest/drivers/led_strip/
Dtlc5971.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/led/led.h>
57 /** GS reference clock edge select bit for OUTXn on-off timing control in FC data */
60 /** Constant-current output enable bit in FC data (0 = output control enabled, 1 = blank). */
69 /** Bit mask for write cmd in data byte 27 */
70 #define TLC5971_BYTE27_WRITE_CMD_MASK GENMASK(7, 2)
72 /** Bit mask for control bits in data byte 27 */
75 /** Bit mask for control bits in data byte 26 */
78 /** Bit mask for global brightness control for color 1 in data byte 26, upper 5 bits of GBC */
81 /** Bit mask for global brightness control for color 1 in data byte 25, lower 2 bits of GBC */
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/Zephyr-latest/samples/bluetooth/hci_uart_3wire/src/
Dmain.c3 * Copyright (c) 2015-2016 Intel Corporation
5 * SPDX-License-Identifier: Apache-2.0
74 #define H5_TX_ACK_PEND 2
81 #define H5_HDR_LEN(hdr) ((((hdr)[1] >> 4) & 0x0f) + ((hdr)[2] << 4))
88 ((hdr)[2] |= (len) >> 4))
123 /* Third byte may change */
129 #define SIGNAL_COUNT 2
151 static int h5_unslip_byte(uint8_t *byte) in h5_unslip_byte() argument
155 if (*byte != SLIP_ESC) { in h5_unslip_byte()
160 count = uart_fifo_read(h5_dev, byte, sizeof(*byte)); in h5_unslip_byte()
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/Zephyr-latest/doc/hardware/peripherals/eeprom/
Dindex.rst3 Electrically Erasable Programmable Read-Only Memory (EEPROM)
9 EEPROMs have an erase block size of 1 byte, a long lifetime, and allow
10 overwriting data on byte-by-byte access.
13 :maxdepth: 2
/Zephyr-latest/subsys/bluetooth/audio/
Dcsip_crypto.h3 * Copyright (c) 2021-2022 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
22 * used in RSIs - Used by the Coordinated Set Identification service and
25 * @param sirk 16 byte LS byte first SIRK
26 * @param r 3 byte LS byte first random value
27 * @param out 3 byte LS byte first output buffer
47 * Part H, Section 2.1 in [2]), and the 64 MSBs of K correspond to the 64 MSBs
49 * K = LTK_64-127 || IRK_0-63
51 * @param k 16-byte key.
73 * Part H, Section 2.1 in [2]), and the 64 MSBs of K correspond to the 64 MSBs
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/Zephyr-latest/subsys/modem/backends/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
28 int "Modem ISR UART delay between first byte received and RECEIVE_READY pipe event"
32 when receiving a byte before sending the RECEIVE_READY pipe event.
36 (<UART receive_buf_size> / 2) / (<UART baud rate> / <UART bits per byte>) * <ms per sec>
37 By default (for the modem_cellular driver): (512 / 2) / (115200 / 10) * 1000 = 22,222 => 20
/Zephyr-latest/dts/bindings/flash_controller/
Dst,stm32-ospi-nor.yaml2 # SPDX-License-Identifier: Apache-2.0
9 mx25lm51245: ospi-nor-flash@70000000 {
10 compatible = "st,stm32-ospi-nor";
12 data-mode = <OSPI_OPI_MODE>; /* access on 8 data lines */
13 data-rate = <OSPI_DTR_TRANSFER>; /* access in DTR */
14 ospi-max-frequency = <DT_FREQ_M(50)>;
18 compatible: "st,stm32-ospi-nor"
20 include: ["flash-controller.yaml", "jedec,jesd216.yaml"]
22 on-bus: ospi
28 ospi-max-frequency:
[all …]
/Zephyr-latest/tests/lib/net_buf/buf/src/
Dmain.c1 /* main.c - Application main entry point */
6 * SPDX-License-Identifier: Apache-2.0
51 uint8_t len[2];
77 struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); in buf_destroy()
86 struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); in fixed_destroy()
95 struct net_buf_pool *pool = net_buf_pool_get(buf->pool_id); in var_destroy()
136 for (i = 0; i < bufs_pool.buf_count - 1; i++) { in ZTEST()
137 frag->frags = net_buf_alloc_len(&bufs_pool, 74, K_NO_WAIT); in ZTEST()
138 zassert_not_null(frag->frags, "Failed to get fragment"); in ZTEST()
139 frag = frag->frags; in ZTEST()
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/Zephyr-latest/subsys/mgmt/mcumgr/transport/src/
Dserial_util.c5 * SPDX-License-Identifier: Apache-2.0
22 if (rx_ctxt->nb != NULL) { in mcumgr_serial_free_rx_ctxt()
23 smp_packet_free(rx_ctxt->nb); in mcumgr_serial_free_rx_ctxt()
24 rx_ctxt->nb = NULL; in mcumgr_serial_free_rx_ctxt()
35 if (rx_ctxt->nb->len < 2) { in mcumgr_serial_extract_len()
36 return -EINVAL; in mcumgr_serial_extract_len()
39 rx_ctxt->pkt_len = net_buf_pull_be16(rx_ctxt->nb); in mcumgr_serial_extract_len()
49 rc = base64_decode(rx_ctxt->nb->data + rx_ctxt->nb->len, in mcumgr_serial_decode_frag()
50 net_buf_tailroom(rx_ctxt->nb), &dec_len, in mcumgr_serial_decode_frag()
53 return -EINVAL; in mcumgr_serial_decode_frag()
[all …]
/Zephyr-latest/drivers/sensor/nxp/fxas21002/
Dfxas21002.h4 * SPDX-License-Identifier: Apache-2.0
32 #define FXAS21002_CTRLREG1_DR_SHIFT 2
38 #define FXAS21002_CTRLREG2_CFG_EN_MASK (1 << 2)
43 #define FXAS21002_BYTES_PER_CHANNEL 2
74 uint8_t *byte);
77 uint8_t byte);
136 uint8_t byte);
140 uint8_t *byte);
155 uint8_t byte);
159 uint8_t *byte);
/Zephyr-latest/drivers/sensor/nxp/fxls8974/
Dfxls8974.h4 * SPDX-License-Identifier: Apache-2.0
66 #define FXLS8974_DATA_ACCEL_Z_OFFSET 2*FXLS8974_BYTES_PER_CHANNEL_NORMAL
74 #define FXLS8974_BYTES_PER_CHANNEL_NORMAL 2
77 #define FXLS8974_MAX_ACCEL_BYTES (FXLS8974_MAX_ACCEL_CHANNELS*2)
106 uint8_t *byte);
109 uint8_t byte);
164 uint8_t byte);
168 uint8_t *byte);
183 uint8_t byte);
187 uint8_t *byte);
/Zephyr-latest/drivers/bluetooth/hci/
Dh5.c1 /* uart_h5.c - UART based Bluetooth driver */
4 * Copyright (c) 2015-2016 Intel Corporation
6 * SPDX-License-Identifier: Apache-2.0
68 #define H5_TX_ACK_PEND 2
75 #define H5_HDR_LEN(hdr) ((((hdr)[1] >> 4) & 0x0f) + ((hdr)[2] << 4))
82 ((hdr)[2] |= (len) >> 4))
135 /* Third byte may change */
141 #define SIGNAL_COUNT (2 * DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT))
147 if (h5->rx_buf) { in h5_reset_rx()
148 net_buf_unref(h5->rx_buf); in h5_reset_rx()
[all …]
/Zephyr-latest/include/zephyr/drivers/misc/ft8xx/
Dft8xx_common.h4 * SPDX-License-Identifier: Apache-2.0
29 * @brief Write 1 byte (8 bits) to FT8xx memory
32 * @param data Byte to write
37 * @brief Write 2 bytes (16 bits) to FT8xx memory
53 * @brief Read 1 byte (8 bits) from FT8xx memory
62 * @brief Read 2 bytes (16 bits) from FT8xx memory
/Zephyr-latest/dts/bindings/retention/
Dzephyr,retention.yaml2 # SPDX-License-Identifier: Apache-2.0
6 64-byte area with 2-byte prefix and 1-byte checksum with 61 usable bytes
10 compatible = "zephyr,memory-region", "mmio-sram";
12 zephyr,memory-region = "RetainedMem";
16 compatible = "zephyr,retained-ram";
18 #address-cells = <1>;
19 #size-cells = <1>;
36 "#address-cells":
43 "#size-cells":
57 type: uint8-array
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/Zephyr-latest/tests/net/socket/socketpair/src/
Dfionread.c4 * SPDX-License-Identifier: Apache-2.0
18 uint8_t byte; in ZTEST_F() local
21 for (int i = 0; i < 2; ++i) { in ZTEST_F()
23 zassert_ok(zsock_ioctl(fixture->sv[i], ZFD_IOCTL_FIONREAD, &avail)); in ZTEST_F()
28 for (int i = 0; i < 2; ++i) { in ZTEST_F()
29 int j = (i + 1) % 2; in ZTEST_F()
31 zassert_equal(1, write(fixture->sv[i], "\x42", 1)); in ZTEST_F()
32 zassert_ok(zsock_ioctl(fixture->sv[j], ZFD_IOCTL_FIONREAD, &avail)); in ZTEST_F()
37 for (int i = 0; i < 2; ++i) { in ZTEST_F()
38 zassert_equal(1, read(fixture->sv[i], &byte, 1)); in ZTEST_F()
[all …]

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