Lines Matching +full:2 +full:- +full:byte
7 * PCH provides SMBus 2.0 - compliant Host Controller.
9 * SPDX-License-Identifier: Apache-2.0
17 /* Host Configuration (HCFG) - Offset 40h, 8 bits */
27 #define PCH_SMBUS_HSTS_DEV_ERROR BIT(2) /* Device Error */
32 #define PCH_SMBUS_HSTS_BYTE_DONE BIT(7) /* Byte Done */
42 #define PCH_SMBUS_HCTL_CMD GENMASK(4, 2) /* Command */
44 #define PCH_SMBUS_HCTL_CMD_QUICK (0 << 2) /* Quick cmd*/
45 #define PCH_SMBUS_HCTL_CMD_BYTE (1 << 2) /* Byte cmd */
46 #define PCH_SMBUS_HCTL_CMD_BYTE_DATA (2 << 2) /* Byte Data cmd */
47 #define PCH_SMBUS_HCTL_CMD_WORD_DATA (3 << 2) /* Word Data cmd */
48 #define PCH_SMBUS_HCTL_CMD_PROC_CALL (4 << 2) /* Process Call cmd */
49 #define PCH_SMBUS_HCTL_CMD_BLOCK (5 << 2) /* Block cmd */
50 #define PCH_SMBUS_HCTL_CMD_I2C_READ (6 << 2) /* I2C Read cmd */
51 #define PCH_SMBUS_HCTL_CMD_BLOCK_PROC (7 << 2) /* Block Process cmd */
53 #define PCH_SMBUS_HCTL_CMD_SET(cmd) (cmd << 2)
57 #define PCH_SMBUS_HCTL_LAST_BYTE BIT(5) /* Last byte block op */
69 /* Set 7-bit address */
100 #define PCH_SMBUS_AUXC_EN_32BUF BIT(1) /* Enable 32-byte buf */
109 #define PCH_SMBUS_SMBC_CLK_CTL BIT(2) /* SMBCLK pin CTL */
119 #define PCH_SMBUS_SCMD_SMBALERT_DIS BIT(2) /* Disable Smbalert */
124 /* Notify Data Low Byte Register (NDLB) */
127 /* Notify Data High Byte Register (NDHB) */
142 reg & PCH_SMBUS_HSTS_BYTE_DONE ? "[Byte Done] " : "", \