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/Zephyr-Core-3.5.0/boards/arm/we_ophelia1ev_nrf52805/
Dwe_ophelia1ev_nrf52805-pinctrl.dtsi5 <NRF_PSEL(TWIM_SCL, 0, 18)>;
12 <NRF_PSEL(TWIM_SCL, 0, 18)>;
21 <NRF_PSEL(SPIM_MISO, 0, 18)>;
29 <NRF_PSEL(SPIM_MISO, 0, 18)>;
40 psels = <NRF_PSEL(UART_RX, 0, 18)>,
49 <NRF_PSEL(UART_RX, 0, 18)>,
/Zephyr-Core-3.5.0/dts/bindings/display/
Dnxp,dcnano-lcdif.yaml30 - "18-bit-config1" # 18-bit configuration 1. RGB666: XXXXXXRR_RRRRGGGG_GGBBBBBB
31 - "18-bit-config2" # 18-bit configuration 2. RGB666: XXRRRRRR_XXGGGGGG_XXBBBBBB
/Zephyr-Core-3.5.0/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdeh029a1.overlay47 10 18 18 08 18 18 08 00
/Zephyr-Core-3.5.0/dts/bindings/mipi-dsi/
Dnxp,imx-mipi-dsi.yaml28 - "18-bit-config-1"
29 - "18-bit-config-2"
39 - "18-bit"
40 - "18-bit-loose"
Dnxp,mipi-dsi-2l.yaml27 - "18-bit-config-1"
28 - "18-bit-config-2"
38 - "18-bit"
39 - "18-bit-loose"
/Zephyr-Core-3.5.0/boards/arm/nrf52840dongle_nrf52840/doc/img/
DnRF52840_dongle_press_reset.svg257 …36,0.24h0.06l0.54,0.18l0.24,0.06h0.36l0.24-0.06h0.24l0.36-0.12l0.18-0.12l0.18-0.06l0.18-0.12l0.12-…
261 …l1.62,0.12h0.24l0.36,0.12l0.18,0.12v0.06l0.18,0.12l0.12,0.18v0.12c0.329,0.538,0.065,0.471,0.24,0.9…
263 l0.18-0.18v-0.06l0.12-0.18l0.06-0.18l0.06-0.24l0.06-0.18l0.06-0.24l0.06-0.12v-0.24l0.06-0.18v-1.8
281 …odd" clip-rule="evenodd" d="M241.35,156.93l-0.06,0.12h-0.06v0.42l0.06,0.12v0.12l0.06,0.06l0.18,0.12
282 …l0.18,0.06l0.24,0.12h0.06l0.24,0.06l0.18,0.06h0.24l0.18,0.06c0.56,0.021,1.411-0.12,1.86-0.48l0.12-…
289 …06h-0.12v0.12l-0.06,0.18l0.06,0.18l0.06,0.12l0.06,0.06h1.08l0.18,0.06l0.24,0.06l0.18,0.06l0.18,0.06
290 …l0.18,0.12l0.24,0.24l0.06,0.12c0.333,0.871,0.057,1.454-0.84,1.74h-0.48l1.86,0.12l0.12-0.18c0.818-1…
291 …h-0.24l0.18-0.06c1.107-0.268,1.418-1.816,0.78-2.64l-0.12-0.18h-0.06c-0.753-0.483-0.21-0.264-0.96-0…
317 l0.18-0.18v-0.36l-0.12-0.24"/>
319 …676,0.066,1.32,0.12,1.98l0.06,0.06v0.24l0.06,0.24l0.12,0.18l0.12,0.36l0.24,0.24l0.12,0.18l0.18,0.12
[all …]
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Dgpio-controller.yaml21 register is 32 bits wide, but only 18 of the bits have a physical
24 all 32 bits, some using 18 and some using 12. In this case, setting
25 "ngpios = <18>;" informs the driver that only the first 18 GPIOs, at
37 GPIO offsets 3, 4, and 10 are not usable, even if ngpios = <18>.
Dsparkfun-pro-micro-header.yaml17 This binding provides a nexus mapping for 18 pins, as depicted below:
26 5 D5 D18/A0 18
/Zephyr-Core-3.5.0/tests/bsim/bluetooth/ll/cis/
Dprj.conf14 CONFIG_BT_ISO_TX_BUF_COUNT=18
38 CONFIG_BT_CTLR_ISO_TX_BUFFERS=18
/Zephyr-Core-3.5.0/tests/lib/cmsis_dsp/filtering/src/
Dmisc_q15.c54 DEFINE_CORRELATE_TEST(14, 18);
59 DEFINE_CORRELATE_TEST(15, 18);
64 DEFINE_CORRELATE_TEST(16, 18);
69 DEFINE_CORRELATE_TEST(17, 18);
74 DEFINE_CORRELATE_TEST(32, 18);
111 DEFINE_CONV_TEST(14, 18);
116 DEFINE_CONV_TEST(15, 18);
121 DEFINE_CONV_TEST(16, 18);
126 DEFINE_CONV_TEST(17, 18);
131 DEFINE_CONV_TEST(32, 18);
/Zephyr-Core-3.5.0/samples/userspace/shared_mem/src/
Dmain.h54 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25}
56 17, 18, 19, 20, 21, 22, 23, 24, 25, 5, 0, 4, 1, 3, 2}
58 15, 14, 17, 16, 19, 18, 21, 20, 23, 22, 25, 24}
/Zephyr-Core-3.5.0/drivers/kscan/
DKconfig.it8xxx216 range 16 18
20 column size for the ITE family is 18.
/Zephyr-Core-3.5.0/samples/sensor/fdc2x1x/boards/
Dnrf9160dk_nrf9160.overlay25 inductance = < 18 >;
34 inductance = <18>;
/Zephyr-Core-3.5.0/boards/arm/nrf9160dk_nrf9160/dts/
Dnrf9160dk_uart1_on_if0_3.dtsi10 psels = <NRF_PSEL(UART_TX, 0, 18)>,
19 psels = <NRF_PSEL(UART_TX, 0, 18)>,
/Zephyr-Core-3.5.0/dts/arm/microchip/
Dmec172xnsz.dtsi83 direct-capable-girqs = <13 14 15 16 17 18 19 20 21 23>;
97 16 17 18 21 22 24 25
108 16 17 18 19 20 21 22 23
119 16 17 18 19 20 21 22 23
130 16 17 18 19 20 21 22 23
141 16 17 18 19 20 21 22 23
169 16 17 18 19 20 22>;
221 18 19 25 26>;
246 12 13 14 15 16 17 18 19
263 girq-id = <18>;
[all …]
/Zephyr-Core-3.5.0/dts/arm/silabs/
Defr32bg22.dtsi24 interrupts = <10 2 18 2>;
44 interrupts = <18 0>;
/Zephyr-Core-3.5.0/tests/drivers/adc/adc_api/boards/
Db_u585i_iot02a_adc4.overlay10 io-channels = <&adc4 18>, <&adc4 19>;
20 reg = <18>;
/Zephyr-Core-3.5.0/soc/x86/apollo_lake/
Dsoc_gpio.h41 #define APL_GPIO_18 18
75 #define APL_GPIO_62 18
125 #define APL_GPIO_PMC_SPI_FS0 18
159 #define APL_GPIO_90 18
208 #define APL_GPIO_148 18
259 #define APL_GPIO_170 18
/Zephyr-Core-3.5.0/samples/boards/nrf/nrfx_prs/boards/
Dnrf9160dk_nrf9160.overlay8 psels = <NRF_PSEL(SPIM_MISO, 0, 18)>;
17 <NRF_PSEL(SPIM_MISO, 0, 18)>;
84 * to the spi1 node (17, 18, and 19).
/Zephyr-Core-3.5.0/boards/arm/frdm_kw41z/
Dfrdm_kw41z.dts49 gpios = <&gpioa 18 GPIO_ACTIVE_LOW>;
90 <1 0 &gpiob 18 0>, /* A1 */
100 <12 0 &gpioc 18 0>, /* D6 */
106 <18 0 &gpioa 17 0>, /* D12 */
107 <19 0 &gpioa 18 0>, /* D13 */
/Zephyr-Core-3.5.0/boards/arm/actinius_icarus_som_dk/
Darduino_connector.dtsi16 <3 0 &gpio0 18 0>, /* A3 */
31 <18 0 &gpio0 14 0>, /* D12 */
43 <3 &adc 5>, /* A3 = P0.18 = AIN5 */
/Zephyr-Core-3.5.0/samples/kernel/condition_variables/simple/
DREADME.rst56 [thread 18] working (0/5)
76 [thread 18] working (1/5)
97 [thread 18] working (2/5)
117 [thread 18] working (3/5)
137 [thread 18] working (4/5)
190 [thread 17] done is now 18. Signalling cond.
192 [thread zephyr_app_main] done is 18 which is < 20 so waiting on cond
193 [thread 18] done is now 19. Signalling cond.
/Zephyr-Core-3.5.0/dts/bindings/input/
Dnuvoton,npcx-kbd.yaml43 default: 18
47 valid range: 1 - 18
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/mec172x/reg/
Dmec172x_vbat.h42 #define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18
73 #define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18
74 #define MCHP_VBATR_CS_DI32_VTR_OFF BIT(18)
/Zephyr-Core-3.5.0/boards/arm/cc1352r1_launchxl/
Dboosterpack_connector.dtsi24 <18 0 &gpio0 11 0>,
34 <36 0 &gpio0 18 0>,

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