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/Zephyr-latest/dts/bindings/display/
Dnxp,dcnano-lcdif.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,dcnano-lcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 backlight-gpios:
18 type: phandle-array
23 data-bus-width:
25 default: "24-bit"
27 - "16-bit-config1" # 16 bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB
28 - "16-bit-config2" # 16 bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB
29 - "16-bit-config3" # 16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX
[all …]
Dnxp,imx-elcdif.yaml1 # Copyright 2022-2023 NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-elcdif"
8 include: [lcd-controller.yaml, pinctrl-device.yaml]
17 data-bus-width:
19 default: "16-bit"
21 - "16-bit"
22 - "8-bit"
23 - "18-bit"
24 - "24-bit"
[all …]
/Zephyr-latest/dts/bindings/mipi-dsi/
Dnxp,imx-mipi-dsi.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,imx-mipi-dsi"
10 include: mipi-dsi-host.yaml
22 dpi-color-coding:
25 - "16-bit-config-1"
26 - "16-bit-config-2"
27 - "16-bit-config-3"
28 - "18-bit-config-1"
29 - "18-bit-config-2"
30 - "24-bit"
[all …]
Dnxp,mipi-dsi-2l.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mipi-dsi-2l"
10 include: mipi-dsi-host.yaml
21 dpi-color-coding:
24 - "16-bit-config-1"
25 - "16-bit-config-2"
26 - "16-bit-config-3"
27 - "18-bit-config-1"
28 - "18-bit-config-2"
29 - "24-bit"
[all …]
/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h6 * SPDX-License-Identifier: Apache-2.0
10 * DesignWare Cores Ethernet Quality-of-Service Databook
76 #define REG_READ(r) sys_read32(p->base_addr + (r))
77 #define REG_WRITE(r, v) sys_write32((v), p->base_addr + (r))
97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_vbat.h4 * SPDX-License-Identifier: Apache-2.0
16 /* Offset 0x00 Power-Fail and Reset Status */
26 #define MCHP_VBATR_PFRS_SYS_RST BIT(2)
27 #define MCHP_VBATR_PFRS_JTAG BIT(3)
28 #define MCHP_VBATR_PFRS_RESETI BIT(4)
29 #define MCHP_VBATR_PFRS_WDT BIT(5)
30 #define MCHP_VBATR_PFRS_SYSRESETREQ BIT(6)
31 #define MCHP_VBATR_PFRS_VBAT_RST BIT(7)
42 #define MCHP_VBATR_CS_DI32_VTR_OFF_POS 18
45 #define MCHP_VBATR_CS_SO_EN BIT(0)
[all …]
Dmec172x_ecia.h4 * SPDX-License-Identifier: Apache-2.0
25 #define MCHP_ECIA_AGGR_BITMAP (BIT(8) | BIT(9) | BIT(10) | BIT(11) | \
26 BIT(12) | BIT(22) | BIT(24) | BIT(25) | \
27 BIT(26))
29 #define MCHP_ECIA_DIRECT_BITMAP (BIT(13) | BIT(14) | BIT(15) | BIT(16) | \
30 BIT(17) | BIT(18) | BIT(19) | BIT(20) | \
31 BIT(21) | BIT(23))
40 * ARM Cortex-M4 NVIC registers
41 * External sources are grouped by 32-bit registers.
42 * MEC172x has 181 external sources requiring 6 32-bit registers.
[all …]
/Zephyr-latest/include/zephyr/math/
Dilog2.h4 * SPDX-License-Identifier: Apache-2.0
25 * This calculates the floor of log2 (integer log2) for 32-bit
31 * nested if-else blocks.
42 (((n) & BIT(31)) == BIT(31)) ? 31 : \
43 (((n) & BIT(30)) == BIT(30)) ? 30 : \
44 (((n) & BIT(29)) == BIT(29)) ? 29 : \
45 (((n) & BIT(28)) == BIT(28)) ? 28 : \
46 (((n) & BIT(27)) == BIT(27)) ? 27 : \
47 (((n) & BIT(26)) == BIT(26)) ? 26 : \
48 (((n) & BIT(25)) == BIT(25)) ? 25 : \
[all …]
/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 200 - 200 - 5ms (default; chip reset value)
17 100 - 100 - 10ms
18 50 - 50 - 20ms
19 25 - 25 - 40ms
20 12.5 - 25/2 - 80ms
21 6.25 - 25/4 - 160ms
[all …]
Dbosch,bmp390.yaml3 # SPDX-License-Identifier: Apache-2.0
7 include: sensor-device.yaml
10 int-gpios:
11 type: phandle-array
17 200 - 200 - 5ms (default; chip reset value)
18 100 - 100 - 10ms
19 50 - 50 - 20ms
20 25 - 25 - 40ms
21 12.5 - 25/2 - 80ms
22 6.25 - 25/4 - 160ms
[all …]
Davago,apds9306.yaml1 # SPDX-License-Identifier: Apache-2.0
3 # Author: Daniel Kampert <DanielKampert@Kampis-Elektroecke.de>
5 description: APDS9306 miniature Surface-Mount Digital Ambient Light Sensor.
10 - sensor-device.yaml
11 - i2c-device.yaml
18 - 18
19 - 9
20 - 6
21 - 3
22 - 1
[all …]
/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h5 * SPDX-License-Identifier: Apache-2.0
46 #define MCP251XFD_RX_FIFO_SIZE_MAX (MCP251XFD_RAM_SIZE - MCP251XFD_RX_FIFO_START_ADDR)
84 /* MPC251x registers - mostly copied from Linux kernel implementation of driver */
89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
105 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
[all …]
Dcan_sja1000_priv.h4 * SPDX-License-Identifier: Apache-2.0
30 #define CAN_SJA1000_ACR2 (18U)
40 #define CAN_SJA1000_XFF_ID2 (18U)
51 #define CAN_SJA1000_MOD_RM BIT(0)
52 #define CAN_SJA1000_MOD_LOM BIT(1)
53 #define CAN_SJA1000_MOD_STM BIT(2)
54 #define CAN_SJA1000_MOD_AFM BIT(3)
55 #define CAN_SJA1000_MOD_SM BIT(4)
58 #define CAN_SJA1000_CMR_TR BIT(0)
59 #define CAN_SJA1000_CMR_AT BIT(1)
[all …]
Dcan_stm32_fdcan.c5 * SPDX-License-Identifier: Apache-2.0
29 * some registers are mapped to other register offsets, and some registers have had their bit fields
33 * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
34 * - CCCR register VMM and UTSU bits are not available.
35 * - TXBC register TFQS, NDTB, and TBSA fields are not available.
39 #define CAN_STM32FD_IR_ARA BIT(23)
40 #define CAN_STM32FD_IR_PED BIT(22)
41 #define CAN_STM32FD_IR_PEA BIT(21)
42 #define CAN_STM32FD_IR_WDI BIT(20)
43 #define CAN_STM32FD_IR_BO BIT(19)
[all …]
/Zephyr-latest/include/zephyr/arch/arm64/
Dcpu.h4 * SPDX-License-Identifier: Apache-2.0
13 #define DAIFSET_FIQ_BIT BIT(0)
14 #define DAIFSET_IRQ_BIT BIT(1)
15 #define DAIFSET_ABT_BIT BIT(2)
16 #define DAIFSET_DBG_BIT BIT(3)
18 #define DAIFCLR_FIQ_BIT BIT(0)
19 #define DAIFCLR_IRQ_BIT BIT(1)
20 #define DAIFCLR_ABT_BIT BIT(2)
21 #define DAIFCLR_DBG_BIT BIT(3)
23 #define DAIF_FIQ_BIT BIT(6)
[all …]
/Zephyr-latest/soc/neorv32/
Dsoc.h4 * SPDX-License-Identifier: Apache-2.0
21 #define NEORV32_SYSINFO_CPU_ZICSR BIT(0)
22 #define NEORV32_SYSINFO_CPU_ZIFENCEI BIT(1)
23 #define NEORV32_SYSINFO_CPU_ZMMUL BIT(2)
24 #define NEORV32_SYSINFO_CPU_ZBB BIT(3)
25 #define NEORV32_SYSINFO_CPU_ZFINX BIT(5)
26 #define NEORV32_SYSINFO_CPU_ZXSCNT BIT(6)
27 #define NEORV32_SYSINFO_CPU_ZXNOCNT BIT(7)
28 #define NEORV32_SYSINFO_CPU_PMP BIT(8)
29 #define NEORV32_SYSINFO_CPU_HPM BIT(9)
[all …]
/Zephyr-latest/soc/intel/intel_adsp/cavs/
D_soc_inthandlers.h3 * SPDX-License-Identifier: Apache-2.0
12 * order (low bits first) and will return a mask of that bit that can
17 #include <xtensa/config/core-isa.h>
22 #error core-isa.h interrupt level does not match dispatcher!
25 #error core-isa.h interrupt level does not match dispatcher!
28 #error core-isa.h interrupt level does not match dispatcher!
31 #error core-isa.h interrupt level does not match dispatcher!
34 #error core-isa.h interrupt level does not match dispatcher!
37 #error core-isa.h interrupt level does not match dispatcher!
40 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/soc/cdns/sample_controller32/include/
D_soc_inthandlers.h4 * SPDX-License-Identifier: Apache-2.0
14 * order (low bits first) and will return a mask of that bit that can
19 #include <xtensa/config/core-isa.h>
24 #error core-isa.h interrupt level does not match dispatcher!
27 #error core-isa.h interrupt level does not match dispatcher!
30 #error core-isa.h interrupt level does not match dispatcher!
33 #error core-isa.h interrupt level does not match dispatcher!
36 #error core-isa.h interrupt level does not match dispatcher!
39 #error core-isa.h interrupt level does not match dispatcher!
42 #error core-isa.h interrupt level does not match dispatcher!
[all …]
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h4 * SPDX-License-Identifier: Apache-2.0
31 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
46 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
48 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v1.h4 * SPDX-License-Identifier: Apache-2.0
30 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
45 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
47 #define SSCR0_ACS BIT(30)
[all …]
Dssp_regs_v3.h4 * SPDX-License-Identifier: Apache-2.0
38 #define SSCR0_DSIZE(x) DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
53 #define SSCR0_FRDC(x) DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
55 #define SSCR0_EFRDC BIT(27)
[all …]
/Zephyr-latest/soc/ite/ec/it8xxx2/
Dilm.c4 * SPDX-License-Identifier: Apache-2.0
20 * IT8xxx2 allows 4-kilobyte blocks of RAM be configured individually as either Instruction- or
32 * address range non-cacheable (which is appropriate because Flash has high latency but RAM is
42 BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must be a power of two");
49 #define SCARH_ENABLE BIT(3)
50 #define SCARH_ADDR_BIT19 BIT(7)
53 * SCAR registers contain 20-bit addresses in three registers, with one set
61 /* Bits 16..18 and 19 of address, plus the enable bit for the entire SCAR; SCARnH */
76 return ((uintptr_t)p & (ILM_BLOCK_SIZE - 1)) == 0; in is_block_aligned()
83 return -EFAULT; /* Not in RAM */ in it8xxx2_configure_ilm_block()
[all …]
/Zephyr-latest/dts/bindings/interrupt-controller/
Dmicrochip,xec-ecia-girq.yaml3 compatible: "microchip,xec-ecia-girq"
14 girq-id:
17 description: GIRQ ID number [0, 18]
23 Bit positions of each source implemented by this GIRQ.
/Zephyr-latest/arch/x86/include/
Dkernel_arch_data.h3 * SPDX-License-Identifier: Apache-2.0
32 #define IV_MACHINE_CHECK 18
41 * EFLAGS/RFLAGS definitions. (RFLAGS is just zero-extended EFLAGS.)
44 #define EFLAGS_IF BIT(9) /* interrupts enabled */
45 #define EFLAGS_DF BIT(10) /* Direction flag */
53 #define CR0_PG BIT(31) /* enable paging */
54 #define CR0_WP BIT(16) /* honor W bit even when supervisor */
56 #define CR4_PSE BIT(4) /* Page size extension (4MB pages) */
57 #define CR4_PAE BIT(5) /* enable PAE */
58 #define CR4_OSFXSR BIT(9) /* enable SSE (OS FXSAVE/RSTOR) */
/Zephyr-latest/soc/nxp/imx/imx8ulp/adsp/
D_soc_inthandlers.h4 * SPDX-License-Identifier: Apache-2.0
13 * order (low bits first) and will return a mask of that bit that can
18 #include <xtensa/config/core-isa.h>
23 #error core-isa.h interrupt level does not match dispatcher!
26 #error core-isa.h interrupt level does not match dispatcher!
29 #error core-isa.h interrupt level does not match dispatcher!
32 #error core-isa.h interrupt level does not match dispatcher!
35 #error core-isa.h interrupt level does not match dispatcher!
38 #error core-isa.h interrupt level does not match dispatcher!
41 #error core-isa.h interrupt level does not match dispatcher!
[all …]

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