Lines Matching +full:18 +full:- +full:bit
5 * SPDX-License-Identifier: Apache-2.0
29 * some registers are mapped to other register offsets, and some registers have had their bit fields
33 * - TEST register SVAL, TXBNS, PVAL, and TXBNP bits are not available.
34 * - CCCR register VMM and UTSU bits are not available.
35 * - TXBC register TFQS, NDTB, and TBSA fields are not available.
39 #define CAN_STM32FD_IR_ARA BIT(23)
40 #define CAN_STM32FD_IR_PED BIT(22)
41 #define CAN_STM32FD_IR_PEA BIT(21)
42 #define CAN_STM32FD_IR_WDI BIT(20)
43 #define CAN_STM32FD_IR_BO BIT(19)
44 #define CAN_STM32FD_IR_EW BIT(18)
45 #define CAN_STM32FD_IR_EP BIT(17)
46 #define CAN_STM32FD_IR_ELO BIT(16)
47 #define CAN_STM32FD_IR_TOO BIT(15)
48 #define CAN_STM32FD_IR_MRAF BIT(14)
49 #define CAN_STM32FD_IR_TSW BIT(13)
50 #define CAN_STM32FD_IR_TEFL BIT(12)
51 #define CAN_STM32FD_IR_TEFF BIT(11)
52 #define CAN_STM32FD_IR_TEFN BIT(10)
53 #define CAN_STM32FD_IR_TFE BIT(9)
54 #define CAN_STM32FD_IR_TCF BIT(8)
55 #define CAN_STM32FD_IR_TC BIT(7)
56 #define CAN_STM32FD_IR_HPM BIT(6)
57 #define CAN_STM32FD_IR_RF1L BIT(5)
58 #define CAN_STM32FD_IR_RF1F BIT(4)
59 #define CAN_STM32FD_IR_RF1N BIT(3)
60 #define CAN_STM32FD_IR_RF0L BIT(2)
61 #define CAN_STM32FD_IR_RF0F BIT(1)
62 #define CAN_STM32FD_IR_RF0N BIT(0)
65 #define CAN_STM32FD_IE_ARAE BIT(23)
66 #define CAN_STM32FD_IE_PEDE BIT(22)
67 #define CAN_STM32FD_IE_PEAE BIT(21)
68 #define CAN_STM32FD_IE_WDIE BIT(20)
69 #define CAN_STM32FD_IE_BOE BIT(19)
70 #define CAN_STM32FD_IE_EWE BIT(18)
71 #define CAN_STM32FD_IE_EPE BIT(17)
72 #define CAN_STM32FD_IE_ELOE BIT(16)
73 #define CAN_STM32FD_IE_TOOE BIT(15)
74 #define CAN_STM32FD_IE_MRAFE BIT(14)
75 #define CAN_STM32FD_IE_TSWE BIT(13)
76 #define CAN_STM32FD_IE_TEFLE BIT(12)
77 #define CAN_STM32FD_IE_TEFFE BIT(11)
78 #define CAN_STM32FD_IE_TEFNE BIT(10)
79 #define CAN_STM32FD_IE_TFEE BIT(9)
80 #define CAN_STM32FD_IE_TCFE BIT(8)
81 #define CAN_STM32FD_IE_TCE BIT(7)
82 #define CAN_STM32FD_IE_HPME BIT(6)
83 #define CAN_STM32FD_IE_RF1LE BIT(5)
84 #define CAN_STM32FD_IE_RF1FE BIT(4)
85 #define CAN_STM32FD_IE_RF1NE BIT(3)
86 #define CAN_STM32FD_IE_RF0LE BIT(2)
87 #define CAN_STM32FD_IE_RF0FE BIT(1)
88 #define CAN_STM32FD_IE_RF0NE BIT(0)
91 #define CAN_STM32FD_ILS_PERR BIT(6)
92 #define CAN_STM32FD_ILS_BERR BIT(5)
93 #define CAN_STM32FD_ILS_MISC BIT(4)
94 #define CAN_STM32FD_ILS_TFERR BIT(3)
95 #define CAN_STM32FD_ILS_SMSG BIT(2)
96 #define CAN_STM32FD_ILS_RXFIFO1 BIT(1)
97 #define CAN_STM32FD_ILS_RXFIFO0 BIT(0)
103 #define CAN_STM32FD_RXGFC_F0OM BIT(9)
104 #define CAN_STM32FD_RXGFC_F1OM BIT(8)
107 #define CAN_STM32FD_RXGFC_RRFS BIT(1)
108 #define CAN_STM32FD_RXGFC_RRFE BIT(0)
129 #define CAN_STM32FD_TXBC_TFQM BIT(24)
259 const struct can_mcan_config *mcan_config = dev->config; in can_stm32fd_read_reg()
260 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom; in can_stm32fd_read_reg()
267 return -ENOTSUP; in can_stm32fd_read_reg()
270 err = can_mcan_sys_read_reg(stm32fd_config->base, remap, &bits); in can_stm32fd_read_reg()
282 /* Group 1 map bits 23-16 (stm32fd) to 29-22 (mcan) */ in can_stm32fd_read_reg()
285 /* Group 2 map bits 15-11 (stm32fd) to 18-14 (mcan) */ in can_stm32fd_read_reg()
288 /* Group 3 map bits 10-4 (stm32fd) to 12-6 (mcan) */ in can_stm32fd_read_reg()
291 /* Group 4 map bits 3-1 (stm32fd) to 4-2 (mcan) */ in can_stm32fd_read_reg()
323 const struct can_mcan_config *mcan_config = dev->config; in can_stm32fd_write_reg()
324 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom; in can_stm32fd_write_reg()
330 return -ENOTSUP; in can_stm32fd_write_reg()
338 /* Group 1 map bits 29-22 (mcan) to 23-16 (stm32fd) */ in can_stm32fd_write_reg()
341 /* Group 2 map bits 18-14 (mcan) to 15-11 (stm32fd) */ in can_stm32fd_write_reg()
342 bits |= ((val & GENMASK(18, 14)) >> 3); in can_stm32fd_write_reg()
344 /* Group 3 map bits 12-6 (mcan) to 10-4 (stm32fd) */ in can_stm32fd_write_reg()
347 /* Group 4 map bits 4-2 (mcan) to 3-1 (stm32fd) */ in can_stm32fd_write_reg()
376 return can_mcan_sys_write_reg(stm32fd_config->base, remap, bits); in can_stm32fd_write_reg()
381 const struct can_mcan_config *mcan_config = dev->config; in can_stm32fd_read_mram()
382 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom; in can_stm32fd_read_mram()
384 return can_mcan_sys_read_mram(stm32fd_config->mram, offset, dst, len); in can_stm32fd_read_mram()
390 const struct can_mcan_config *mcan_config = dev->config; in can_stm32fd_write_mram()
391 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom; in can_stm32fd_write_mram()
393 return can_mcan_sys_write_mram(stm32fd_config->mram, offset, src, len); in can_stm32fd_write_mram()
398 const struct can_mcan_config *mcan_config = dev->config; in can_stm32fd_clear_mram()
399 const struct can_stm32fd_config *stm32fd_config = mcan_config->custom; in can_stm32fd_clear_mram()
401 return can_mcan_sys_clear_mram(stm32fd_config->mram, offset, len); in can_stm32fd_clear_mram()
412 return -EIO; in can_stm32fd_get_core_clock()
415 if (FDCAN_CONFIG->CKDIV == 0) { in can_stm32fd_get_core_clock()
418 *rate = rate_tmp / (FDCAN_CONFIG->CKDIV << 1); in can_stm32fd_get_core_clock()
427 const struct can_mcan_config *mcan_cfg = dev->config; in can_stm32fd_clock_enable()
428 const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom; in can_stm32fd_clock_enable()
432 return -ENODEV; in can_stm32fd_clock_enable()
435 if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) { in can_stm32fd_clock_enable()
437 (clock_control_subsys_t)&stm32fd_cfg->pclken[1], in can_stm32fd_clock_enable()
445 ret = clock_control_on(clk, (clock_control_subsys_t)&stm32fd_cfg->pclken[0]); in can_stm32fd_clock_enable()
450 if (stm32fd_cfg->clock_divider != 0) { in can_stm32fd_clock_enable()
452 FDCAN_CONFIG->CKDIV = stm32fd_cfg->clock_divider >> 1; in can_stm32fd_clock_enable()
460 const struct can_mcan_config *mcan_cfg = dev->config; in can_stm32fd_init()
461 const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom; in can_stm32fd_init()
466 ret = pinctrl_apply_state(stm32fd_cfg->pcfg, PINCTRL_STATE_DEFAULT); in can_stm32fd_init()
505 stm32fd_cfg->config_irq(); in can_stm32fd_init()