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/Zephyr-latest/dts/bindings/display/
Dnxp,dcnano-lcdif.yaml25 default: "24-bit"
27 - "16-bit-config1" # 16 bit configuration 1. RGB565: XXXXXXXX_RRRRRGGG_GGGBBBBB
28 - "16-bit-config2" # 16 bit configuration 2. RGB565: XXXRRRRR_XXGGGGGG_XXXBBBBB
29 - "16-bit-config3" # 16-bit configuration 3. RGB565: XXRRRRRX_XXGGGGGG_XXBBBBBX
30 - "18-bit-config1" # 18-bit configuration 1. RGB666: XXXXXXRR_RRRRGGGG_GGBBBBBB
31 - "18-bit-config2" # 18-bit configuration 2. RGB666: XXRRRRRR_XXGGGGGG_XXBBBBBB
32 - "24-bit" # 24 Bit
34 LCD data bus width. The default is set to the reset value of 24-bit
Dnxp,imx-elcdif.yaml19 default: "16-bit"
21 - "16-bit"
22 - "8-bit"
23 - "18-bit"
24 - "24-bit"
26 LCD data bus width. The default is set to the reset value of 16-bit
/Zephyr-latest/drivers/dai/intel/ssp/
Dssp_regs_v2.h38 #define SSCR0_ECS BIT(6)
39 #define SSCR0_SSE BIT(7)
42 #define SSCR0_EDSS BIT(20)
43 #define SSCR0_NCS BIT(21)
44 #define SSCR0_RIM BIT(22)
45 #define SSCR0_TIM BIT(23)
48 #define SSCR0_ACS BIT(30)
49 #define SSCR0_MOD BIT(31)
52 #define SSCR1_RIE BIT(0)
53 #define SSCR1_TIE BIT(1)
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Dssp_regs_v3.h45 #define SSCR0_RSVD1 BIT(6)
46 #define SSCR0_SSE BIT(7)
49 #define SSCR0_EDSS BIT(20)
50 #define SSCR0_RSVD2 BIT(21)
51 #define SSCR0_RIM BIT(22)
52 #define SSCR0_TIM BIT(23)
55 #define SSCR0_EFRDC BIT(27)
56 #define SSCR0_EFRDC2 BIT(28)
58 #define SSCR0_ACS BIT(30)
59 #define SSCR0_MOD BIT(31)
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Dssp_regs_v1.h37 #define SSCR0_ECS BIT(6)
38 #define SSCR0_SSE BIT(7)
41 #define SSCR0_EDSS BIT(20)
42 #define SSCR0_NCS BIT(21)
43 #define SSCR0_RIM BIT(22)
44 #define SSCR0_TIM BIT(23)
47 #define SSCR0_ACS BIT(30)
48 #define SSCR0_MOD BIT(31)
51 #define SSCR1_RIE BIT(0)
52 #define SSCR1_TIE BIT(1)
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/Zephyr-latest/include/zephyr/sys/
Dbyteorder.h20 #define BSWAP_24(x) ((uint32_t) ((((x) >> 16) & 0xff) | \
22 (((x) & 0xff) << 16)))
28 (((x) >> 16) & 0xff00) | \
30 (((x) & 0xff00) << 16) | \
48 * @brief Convert 16-bit integer from little-endian to host endianness.
50 * @param val 16-bit integer in little-endian format.
52 * @return 16-bit integer in host endianness.
56 * @brief Convert 16-bit integer from host endianness to little-endian.
58 * @param val 16-bit integer in host endianness.
60 * @return 16-bit integer in little-endian format.
[all …]
Dsys_io.h48 * @brief Output a 16 bits to an I/O port
50 * This function writes a 16 bits to the given port.
52 * @param data the 16 bits to write
53 * @param port the port address where to write the 16 bits
58 * @brief Input 16 bits from an I/O port
60 * This function reads 16 bits from the port.
62 * @param port the port address from where to read the 16 bits
64 * @return the 16 bits read
89 * @fn static inline void sys_io_set_bit(io_port_t port, unsigned int bit)
90 * @brief Set the designated bit from port to 1
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/Zephyr-latest/include/zephyr/bluetooth/
Dbyteorder.h26 /** @brief Encode 16-bit value into array values in little-endian format.
28 * Helper macro to encode 16-bit values into comma separated values.
32 * @param _v 16-bit integer in host endianness.
34 * @return The comma separated values for the 16-bit value.
40 /** @brief Encode 24-bit value into array values in little-endian format.
42 * Helper macro to encode 24-bit values into comma separated values.
46 * @param _v 24-bit integer in host endianness.
48 * @return The comma separated values for the 24-bit value.
52 (((_v) >> 16) & 0xFFU) \
54 /** @brief Encode 32-bit value into array values in little-endian format.
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/Zephyr-latest/subsys/bluetooth/crypto/
Dbt_crypto.h14 * @brief Cypher based Message Authentication Code (CMAC) with AES 128 bit
18 * @param[in] key 128-bit key
33 * @param[in] u 256-bit
34 * @param[in] v 256-bit
35 * @param[in] x 128-bit key
36 * @param[in] z 8-bit
42 int bt_crypto_f4(const uint8_t *u, const uint8_t *v, const uint8_t *x, uint8_t z, uint8_t res[16]);
49 * @param[in] w 256-bit
50 * @param[in] n1 128-bit
51 * @param[in] n2 128-bit
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/Zephyr-latest/dts/bindings/sensor/
Dbosch,bmp388.yaml23 1.563 - 25/16 - 640ms
58 1 sample, 16-bit, 2.64 Pa
59 2 samples, 17-bit, 1.32 Pa
60 4 samples, 18-bit, 0.66 Pa (default; chip reset value)
61 8 samples, 19-bit, 0.33 Pa
62 16 samples, 20-bit, 0.17 Pa
63 32 Samples, 21-bit, 0.085 Pa
70 - 16
78 1 sample, 16-bit, .0050 C (default; chip reset value)
79 2 samples, 17-bit, .0025 C
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Dbosch,bmp390.yaml24 1.563 - 25/16 - 640ms
59 1 sample, 16-bit, 2.64 Pa
60 2 samples, 17-bit, 1.32 Pa
61 4 samples, 18-bit, 0.66 Pa (default; chip reset value)
62 8 samples, 19-bit, 0.33 Pa
63 16 samples, 20-bit, 0.17 Pa
64 32 Samples, 21-bit, 0.085 Pa
71 - 16
79 1 sample, 16-bit, .0050 C (default; chip reset value)
80 2 samples, 17-bit, .0025 C
[all …]
Dti,ina219.yaml28 0 = 16 V FSR
33 Should the expected bus voltage be below 16V set this to 0.
61 0 = 9 bit -> 84 µs
62 1 = 10 bit -> 148 µs
63 2 = 11 bit -> 276 µs
64 3 = 12 bit -> 532 µs
65 9 = 12 bit - 2 sample averaging -> 1.06 ms
66 10 = 12 bit - 4 sample averaging -> 2.13 ms
67 11 = 12 bit - 8 sample averaging -> 4.26 ms
68 12 = 12 bit - 16 sample averaging -> 8.51 ms
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/Zephyr-latest/drivers/serial/
Duart_rzt2m.h12 #define MAX_FIFO_DEPTH 16
36 #define CCR0_MASK_RE BIT(0)
37 #define CCR0_MASK_TE BIT(4)
38 #define CCR0_MASK_DCME BIT(9)
39 #define CCR0_MASK_IDSEL BIT(10)
40 #define CCR0_MASK_RIE BIT(16)
41 #define CCR0_MASK_TIE BIT(20)
42 #define CCR0_MASK_TEIE BIT(21)
43 #define CCR0_MASK_SSE BIT(24)
45 #define CCR1_MASK_CTSE BIT(0)
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/Zephyr-latest/drivers/ethernet/
Deth_dwmac_priv.h97 #define MAC_CONF_ARPEN BIT(31)
99 #define MAC_CONF_IPC BIT(27)
101 #define MAC_CONF_GPSLCE BIT(23)
102 #define MAC_CONF_S2KP BIT(22)
103 #define MAC_CONF_CST BIT(21)
104 #define MAC_CONF_ACS BIT(20)
105 #define MAC_CONF_WD BIT(19)
106 #define MAC_CONF_BE BIT(18)
107 #define MAC_CONF_JD BIT(17)
108 #define MAC_CONF_JE BIT(16)
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/Zephyr-latest/drivers/can/
Dcan_mcp251xfd.h89 #define MCP251XFD_REG_CON_ABAT BIT(27)
100 #define MCP251XFD_REG_CON_TXQEN BIT(20)
101 #define MCP251XFD_REG_CON_STEF BIT(19)
102 #define MCP251XFD_REG_CON_SERR2LOM BIT(18)
103 #define MCP251XFD_REG_CON_ESIGM BIT(17)
104 #define MCP251XFD_REG_CON_RTXAT BIT(16)
105 #define MCP251XFD_REG_CON_BRSDIS BIT(12)
106 #define MCP251XFD_REG_CON_BUSY BIT(11)
112 #define MCP251XFD_REG_CON_WAKFIL BIT(8)
113 #define MCP251XFD_REG_CON_PXEDIS BIT(6)
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/Zephyr-latest/dts/bindings/mipi-dsi/
Dnxp,imx-mipi-dsi.yaml25 - "16-bit-config-1"
26 - "16-bit-config-2"
27 - "16-bit-config-3"
28 - "18-bit-config-1"
29 - "18-bit-config-2"
30 - "24-bit"
33 the 24-bit d bus, as specified by the DPI specification.
38 - "16-bit"
39 - "18-bit"
40 - "18-bit-loose"
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Dnxp,mipi-dsi-2l.yaml24 - "16-bit-config-1"
25 - "16-bit-config-2"
26 - "16-bit-config-3"
27 - "18-bit-config-1"
28 - "18-bit-config-2"
29 - "24-bit"
32 the 24-bit d bus, as specified by the DPI specification.
37 - "16-bit"
38 - "18-bit"
39 - "18-bit-loose"
[all …]
/Zephyr-latest/drivers/spi/
Dspi_pw.h41 #define PW_SPI_CTRLR0_SSE_BIT BIT(7)
42 #define PW_SPI_CTRLR0_EDSS_BIT BIT(20)
43 #define PW_SPI_CTRLR0_RIM_BIT BIT(22)
44 #define PW_SPI_CTRLR0_TIM_BIT BIT(23)
45 #define PW_SPI_CTRLR0_MOD_BIT BIT(31)
71 #define PW_SPI_CTRL1_RIE_BIT BIT(0)
72 #define PW_SPI_CTRL1_TIE_BIT BIT(1)
73 #define PW_SPI_CTRL1_LBM_BIT BIT(2)
74 #define PW_SPI_CTRL1_SPO_BIT BIT(3)
75 #define PW_SPI_CTRL1_SPH_BIT BIT(4)
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Dspi_andes_atcspi200.h44 #define TFMAT_CPHA_MSK BIT(0)
45 #define TFMAT_CPOL_MSK BIT(1)
46 #define TFMAT_SLVMODE_MSK BIT(2)
47 #define TFMAT_LSB_MSK BIT(3)
48 #define TFMAT_DATA_MERGE_MSK BIT(7)
50 #define TFMAT_ADDR_LEN_MSK GENMASK(18, 16)
66 #define IEN_RX_FIFO_MSK BIT(2)
67 #define IEN_TX_FIFO_MSK BIT(3)
68 #define IEN_END_MSK BIT(4)
71 #define INTST_RX_FIFO_INT_MSK BIT(2)
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/Zephyr-latest/drivers/sdhc/
Dsdhc_cdns_ll.h10 #define CDNS_HRS09_PHY_SW_RESET BIT(0)
11 #define CDNS_HRS09_PHY_INIT_COMP BIT(1)
12 #define CDNS_HRS09_EXT_WR_MODE BIT(3)
13 #define CDNS_HRS09_RDCMD_EN_BIT BIT(15)
14 #define CDNS_HRS09_RDDATA_EN_BIT BIT(16)
18 #define CDNS_HRS09_RDDATA_EN(x) ((x) << 16)
21 #define CDNS_HRS00_SWR BIT(0)
27 #define CDNS_SRS09_STAT_DAT_BUSY BIT(2)
28 #define CDNS_SRS09_CI BIT(16)
31 #define LEDC BIT(0)
[all …]
/Zephyr-latest/soc/microchip/mec/mec172x/reg/
Dmec172x_qspi.h17 #define MCHP_QMSPI_MAX_DESCR 16u
130 #define MCHP_QMSPI_M_ACTIVATE BIT(0)
131 #define MCHP_QMSPI_M_SRST BIT(1)
132 #define MCHP_QMSPI_M_SAF_DMA_MODE_EN BIT(2)
133 #define MCHP_QMSPI_M_LDMA_RX_EN BIT(3)
134 #define MCHP_QMSPI_M_LDMA_TX_EN BIT(4)
137 #define MCHP_QMSPI_M_CPOL_CLK_IDLE_HI BIT(8)
143 #define MCHP_QMSPI_M_CPHA_MOSI_CE2 BIT(9)
149 #define MCHP_QMSPI_M_CPHA_MISO_CE2 BIT(10)
170 #define MCHP_QMSPI_M_FDIV_POS 16u
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Dmec172x_i2c_smb.h36 * Size 8-bit
40 #define MCHP_I2C_SMB_CTRL_ACK BIT(0)
41 #define MCHP_I2C_SMB_CTRL_STO BIT(1)
42 #define MCHP_I2C_SMB_CTRL_STA BIT(2)
43 #define MCHP_I2C_SMB_CTRL_ENI BIT(3)
45 #define MCHP_I2C_SMB_CTRL_ESO BIT(6)
46 #define MCHP_I2C_SMB_CTRL_PIN BIT(7)
49 #define MCHP_I2C_SMB_STS_NBB BIT(0)
50 #define MCHP_I2C_SMB_STS_LAB BIT(1)
51 #define MCHP_I2C_SMB_STS_AAS BIT(2)
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/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_timers.h25 * 32-bit R/W
26 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
32 * 32-bit R/W
33 * 16-bit Basic timers: bits[15:0]=R/W, bits[31:15]=RO=0
54 #define MCHP_BTMR_CTRL_PRESCALE_POS 16u
74 /** @brief Basic Timer(32 and 16 bit) registers. Total size = 20(0x14) bytes */
87 * Set count resolution in bit[0]
93 #define MCHP_HTMR_CTRL_RESOL_MASK BIT(MCHP_HTMR_CTRL_EN_POS)
95 #define MCHP_HTMR_CTRL_RESOL_125MS BIT(MCHP_HTMR_CTRL_EN_POS)
117 /* Control register at offset 0x00. Must use 32-bit access */
[all …]
/Zephyr-latest/include/zephyr/drivers/mfd/
Dnpm1300.h47 * @param base Register base address (bits 15..8 of 16-bit address)
48 * @param offset Register offset address (bits 7..0 of 16-bit address)
61 * @param base Register base address (bits 15..8 of 16-bit address)
62 * @param offset Register offset address (bits 7..0 of 16-bit address)
73 * @param base Register base address (bits 15..8 of 16-bit address)
74 * @param offset Register offset address (bits 7..0 of 16-bit address)
85 * @param base Register base address (bits 15..8 of 16-bit address)
86 * @param offset Register offset address (bits 7..0 of 16-bit address)
99 * @param base Register base address (bits 15..8 of 16-bit address)
100 * @param offset Register offset address (bits 7..0 of 16-bit address)
/Zephyr-latest/drivers/sensor/jedec/jc42/
Djc42.h27 /* 16 bits control configuration and state.
29 * * Bit 0 controls alert signal output mode
30 * * Bit 1 controls interrupt polarity
31 * * Bit 2 disables upper and lower threshold checking
32 * * Bit 3 enables alert signal output
33 * * Bit 4 records alert status
34 * * Bit 5 records interrupt status
35 * * Bit 6 locks the upper/lower window registers
36 * * Bit 7 locks the critical register
37 * * Bit 8 enters shutdown mode
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