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/Zephyr-Core-3.5.0/drivers/pinctrl/
Dpinctrl_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
21 /* gpio port control register (byte mapping to pin) */
43 * KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register
44 * (bit mapping to pin)
47 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port control register */
50 * KSO push-pull/open-drain bit of KSO[15:0] control register
55 * KSI/KSO pullup bit of KSI[7:0]/KSO[15:0] control register
71 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
72 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set()
73 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
[all …]
/Zephyr-Core-3.5.0/dts/bindings/pinctrl/
Dite,it8xxx2-pinctrl-func.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ITE IT8XXX2 pin controller function node
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
[all …]
Dst,stm32-pinctrl.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32 Pin controller Node
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
22 description: Remaps the PA11 pin to operate as PA9 pin.
25 remap-pa12:
27 description: Remaps the PA12 pin to operate as PA10 pin.
[all …]
/Zephyr-Core-3.5.0/dts/bindings/pwm/
Dinfineon,xmc4xxx-ccu4-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
10 A channel is connected to a particular gpio pin, which are defined
12 dts/arm/infineon/xmc4xxx_xxx-pinctrl.dtsi
24 The pwm ccu4 node must define the slice-prescaler values and the pinctrl nodes:
26 slice-prescaler = <15 15 15 15>;
27 pinctrl-0 = <&pwm_out_p1_1_ccu40_ch2>;
28 pinctrl-names = "default";
39 The pin should be configured with drive-push-pull bool option and hwctrl should be set
40 to disabled. The drive-strength field can be set to any of the supported values:
42 drive-strength = "strong-medium-edge";
[all …]
Dinfineon,xmc4xxx-ccu8-pwm.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The PWM CCU8 module can automatically generate a high-side
8 and a low-side PWM signal, where the two signals are complementary
11 The module supports adding a dead time between the high-side and
12 low-side PWM signals.
15 transitions from 0 to 1, preventing the high-side and low-side
20 two channels. A channel consists of a corresponding high-side
21 and low-side PWM signal.
25 defined by the 'slice-prescaler' property. Additionally, each
38 slice-prescaler = <15 15 15 15>;
[all …]
/Zephyr-Core-3.5.0/dts/bindings/led/
Dgpio-leds.yaml2 # SPDX-License-Identifier: Apache-2.0
7 gpio-leds node.
13 compatible = "gpio-leds";
21 gpios = <&gpio1 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
28 - led_0 is pin 1 on gpio0. The LED is on when the pin is low,
29 and off when the pin is high.
30 - led_1 is pin 2 on gpio0. The LED is on when the pin is high,
32 - led_2 is pin 15 on gpio1. The LED is on when the pin is low,
33 and the pin's internal pull-up resistor should be enabled.
35 compatible: "gpio-leds"
[all …]
/Zephyr-Core-3.5.0/include/zephyr/dt-bindings/pinctrl/
Dnumicro-pinctrl.h4 * SPDX-License-Identifier: Apache-2.0
18 * @brief Pin configuration configuration bit field.
22 * - mfp [ 0 : 3 ]
23 * - pin [ 4 : 7 ]
24 * - port [ 8 : 11 ]
27 * @param pin Pin (0..15)
28 * @param mfp Multi-function value (0..15)
30 #define NUMICRO_PINMUX(port, pin, mfp) \ argument
31 (((((port) - 'A') & NUMICRO_PORT_MASK) << NUMICRO_PORT_SHIFT) | \
32 (((pin) & NUMICRO_PIN_MASK) << NUMICRO_PIN_SHIFT) | \
Dgecko-pinctrl-s1.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
[all …]
Dgecko-pinctrl.h3 * SPDX-License-Identifier: Apache-2.0
10 * The whole GECKO_pin configuration information is encoded in a 32-bit bitfield
13 * - 31..24: Pin function.
14 * - 23..16: Reserved.
15 * - 15..8: Port for UART_RX/UART_TX functions.
16 * - 7..0: Pin number for UART_RX/UART_TX functions.
17 * - 15..8: Reserved for UART_LOC function.
18 * - 7..0: Loc for UART_LOC function.
31 /** Position of the pin field. */
33 /** Mask for the pin field. */
[all …]
/Zephyr-Core-3.5.0/dts/bindings/gpio/
Darduino-nano-header-r3.yaml2 # SPDX-License-Identifier: Apache-2.0
9 * A 15-pin header with mostly digital signals. The additional NRST (pin3)
10 and GND (pin 4) pins are not exposed by this binding.
11 * A 15-pin Analog Input and power supply header. This has analog input
19 1 D1 VIN -
20 0 D0 GND -
21 - RESET RESET -
22 - GND 5V -
29 8 D8 A1/D15 15
31 10 D10 AREF -
[all …]
Darduino-mkr-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 * One side of the 14-pin header is analog inputs and digital signals.
10 A1 to A6 is Analog input. The outside pin is AREF.
11 A0 that is next to AREF used as a DAC output pin too.
12 D0-D5 is a digital output.
13 * The other side 14-pin header is power supplies and peripheral interface.
14 There are 5V and VCC power supply, GND, and RESET pin. UART, I2C,
18 through 14 correspond to D0 through D21, and parent pins 15 through 21
21 - AREF 5V -
22 15 A0/D15/DAC0 VIN -
[all …]
Datmel-xplained-pro-header.yaml2 # SPDX-License-Identifier: Apache-2.0
7 The Xplained Pro layout provide a standard 20 pin header. A board can have
9 names EXTn where n ϵ [1…7], n is determined by which ID pin is connected
28 https://www.microchip.com/development-tools/xplained-boards
29 …http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-42091-Atmel-Xplained-Pro-Hardware-Developmen…
35 Bind Pin Name Pin Pin Pin Name Bind
37 0 ADC(+) 3 4 ADC(-) 1
39 4 PWM(+) 7 8 PWM(-) 5
43 12 SPI(CS0) 15 16 SPI(MOSI) 13
44 14 SPI(MISO) 17 18 SPI(SCK) 15
[all …]
Dparticle-gen3-header.yaml2 # SPDX-License-Identifier: Apache-2.0
8 "shields" but use a different orientation and pin numbering scheme.
11 * A 12-pin header on the right. 9 pins on this header are exposed
13 * A 16-pin header. 13 pins on this header are exposed by this
17 0 through 8 correspond to the pins on the 12-pin header, starting
19 16-pin header, skipping the bottom pin then assigning 9 through 19,
20 skipping over GND, and replacing the lower 3V3 with pin 20. The
24 - 3V3
26 - GND
27 19 ADC0 LiPo+ -
[all …]
Dti,boosterpack-header.yaml2 # SPDX-License-Identifier: Apache-2.0
9 BoosterPack plug-in modules are available in 20 and 40 pin variants. The
10 20 pin variant has two 10 x 1 pin headers and the 40 pin variant has two
11 10 x 2 pin headers. Both variants are compatible and stackable.
13 The pins of the 20 pin variant and the outer row of the 40 pin variant are
14 numbered 1 through 20. The inner rows of the 40 pin variant are numbered 21
22 6 Analog 26 Analog 35 GPIO 15 SPI MOSI
32 compatible: "ti,boosterpack-header"
34 include: [gpio-nexus.yaml, base.yaml]
/Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/boards/
Dgd32f450i_eval.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-basic-api";
10 /* unplug camera from JP27 and bridge D0-D1 (pins 16 and 15) */
11 out-gpios = <&gpioc 6 0>; /* DCI D0 (JP27 pin 16)*/
12 in-gpios = <&gpioc 7 0>; /* DCI D1 (JP27 pin 15) */
Dudoo_neo_full_m4.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "test-gpio-basic-api";
10 out-gpios = <&gpio5 14 0>; /* J4 pin 4 */
11 in-gpios = <&gpio5 15 0>; /* J4 pin 3 */
Dmec15xxevb_assy6853.overlay5 * SPDX-License-Identifier: Apache-2.0
10 compatible = "test-gpio-basic-api";
13 * Remove jumpers on JP31 to disconnect pull-up resistor.
14 * Also remove jumpers on JP41 (1-2, 3-4) as the LEDs
15 * are connected to pull-up resistors also.
17 in-gpios = <MCHP_GPIO_DECODE_156 0>; /* GPIO_156, JP31 Pin 13 */
18 out-gpios = <MCHP_GPIO_DECODE_157 0>; /* GPIO_157, JP31 Pin 15 */
/Zephyr-Core-3.5.0/drivers/gpio/
Dgpio_kscan_ite_it8xxx2.c4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
21 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio output enable register (bit mapping to pin) */
23 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio control register (bit mapping to pin) */
25 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data register (bit mapping to pin) */
27 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio data mirror register (bit mapping to pin) */
29 /* KSI[7:0]/KSO[15:8]/KSO[7:0] port gpio open drain register (bit mapping to pin) */
39 gpio_pin_t pin, in gpio_kscan_it8xxx2_configure() argument
42 const struct gpio_kscan_cfg *const config = dev->config; in gpio_kscan_it8xxx2_configure()
43 volatile uint8_t *reg_ksi_kso_gctrl = config->reg_ksi_kso_gctrl; in gpio_kscan_it8xxx2_configure()
[all …]
/Zephyr-Core-3.5.0/dts/bindings/sensor/
Dti,ina23x-common.yaml4 # SPDX-License-Identifier: Apache-2.0
7 include: [sensor-device.yaml, i2c-device.yaml]
10 current-lsb-microamps:
17 current-lsb(A) = maximum expected current(A) / 2^15
19 (sensor has 15 bits). For example, if maximum expected current is 15A:
21 current-lsb(A) = 15A / 2^15 ~= 457uA
27 rshunt-micro-ohms:
32 alert-gpios:
33 type: phandle-array
34 description: Alert pin
/Zephyr-Core-3.5.0/soc/arm/xilinx_zynq7000/common/
Dpinctrl_soc.h4 * SPDX-License-Identifier: Apache-2.0
52 /* MIO pin function multiplexing (from Xilinx UG585 v1.13, B.28 SLCR) */
86 /* MIO SDIO CD/WP pin selection (from Xilinx UG585 v1.13, B.28 SLCR) */
107 /* MIO pin numbers */
123 #define MIO15 15
163 /* MIO pin groups (from Xilinx UG585 v1.13, table 2-4 "MIO-at-a-Glance") */
187 #define MIO_GROUP_SPI1_0_SS2_PINS 15
203 #define MIO_GROUP_SDIO1_0_GRP_PINS 10, 11, 12, 13, 14, 15
211 #define MIO_GROUP_SMC0_NOR_PINS 0, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, \
219 #define MIO_GROUP_CAN0_1_GRP_PINS 14, 15
[all …]
/Zephyr-Core-3.5.0/soc/arm/nxp_imx/rt5xx/
Dpower.c4 * SPDX-License-Identifier: Apache-2.0
26 /* Backup Pin configuration. */ in set_deepsleep_pin_config()
27 isp_pin[0] = IOPCTL->PIO[1][15]; in set_deepsleep_pin_config()
28 isp_pin[1] = IOPCTL->PIO[3][28]; in set_deepsleep_pin_config()
29 isp_pin[2] = IOPCTL->PIO[3][29]; in set_deepsleep_pin_config()
31 /* Disable ISP Pin pull-ups and input buffers to avoid current leakage */ in set_deepsleep_pin_config()
32 IOPCTL->PIO[1][15] = 0; in set_deepsleep_pin_config()
33 IOPCTL->PIO[3][28] = 0; in set_deepsleep_pin_config()
34 IOPCTL->PIO[3][29] = 0; in set_deepsleep_pin_config()
39 /* Restore the Pin configuration. */ in restore_deepsleep_pin_config()
[all …]
/Zephyr-Core-3.5.0/tests/drivers/gpio/gpio_basic_api/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
30 out_dev->name, in_dev->name); in board_setup()
37 * Configure pin mux. in board_setup()
42 if (PIN_IN != 15) { in board_setup()
43 printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15); in board_setup()
48 printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14); in board_setup()
52 /* Configure pin RGMII2_RD2 as GPIO5_IO14. */ in board_setup()
62 /* Configure pin RGMII2_RD3 as GPIO5_IO15. */ in board_setup()
97 /* This functions allows to programmatically short-circuit SOC GPIO pins */ in board_setup()
/Zephyr-Core-3.5.0/soc/arm/microchip_mec/common/
Dsoc_i2c.h3 * SPDX-License-Identifier: Apache-2.0
14 /* 144-pin package I2C port masks */
36 #define MCHP_I2C_PORT_15 15
40 * Read pin states of specified I2C port.
42 * lines b[0]=SCL pin state at pad, b[1]=SDA pin state at pad
43 * Returns 0 success or -EINVAL if port is not support or lines is NULL.
/Zephyr-Core-3.5.0/boards/arm/v2m_beetle/
Dpinmux.c4 * SPDX-License-Identifier: Apache-2.0
18 * are responsible for pin muxing, input/output, pull-up, etc.
24 * pin numbers:
25 * Pins 0 - 15 are for GPIO0
26 * Pins 16 - 31 are for GPIO1
29 * compliant pin out.
102 gpio_0 |= (1<<15); /* Shield 0 I2C SCL SBCON2 */ in arm_v2m_beetle_pinmux_defaults()
108 CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0; in arm_v2m_beetle_pinmux_defaults()
127 CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1; in arm_v2m_beetle_pinmux_defaults()
129 /* Set the ARD_PWR_EN GPIO1[15] as an output */ in arm_v2m_beetle_pinmux_defaults()
[all …]
/Zephyr-Core-3.5.0/soc/arm/silabs_exx32/efm32jg12b/
Dsoc_pinmap.h3 * SPDX-License-Identifier: Apache-2.0
7 * @brief Silabs EFM32JG12B MCU pin definitions.
9 * This file contains pin configuration data required by different MCU
31 #define PIN_SWO {gpioPortD, 15, gpioModePushPull, 1}
35 #error ("Invalid SWO pin location")

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