1 /*
2 * Copyright (c) 2016 Intel Corporation
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7
8 #include "test_gpio.h"
9
10 /* Grotesque hack for pinmux boards */
11 #if defined(CONFIG_BOARD_RV32M1_VEGA)
12 #include <fsl_port.h>
13 #elif defined(CONFIG_BOARD_UDOO_NEO_FULL_M4)
14 #include "device_imx.h"
15 #elif defined(CONFIG_BOARD_MIMXRT1050_EVK)
16 #include <fsl_iomuxc.h>
17 #elif defined(CONFIG_BOARD_NRF52_BSIM)
18 #include <NRF_GPIO.h>
19 #endif
20
board_setup(void)21 static void board_setup(void)
22 {
23 #if DT_NODE_HAS_STATUS(DT_INST(0, test_gpio_basic_api), okay)
24 /* PIN_IN and PIN_OUT must be on same controller. */
25 const struct device *const in_dev = DEVICE_DT_GET(DEV_OUT);
26 const struct device *const out_dev = DEVICE_DT_GET(DEV_IN);
27
28 if (in_dev != out_dev) {
29 printk("FATAL: output controller %s != input controller %s\n",
30 out_dev->name, in_dev->name);
31 k_panic();
32 }
33 #endif
34
35 #if defined(CONFIG_BOARD_UDOO_NEO_FULL_M4)
36 /*
37 * Configure pin mux.
38 * The following code needs to configure the same GPIOs which were
39 * selected as test pins in device tree.
40 */
41
42 if (PIN_IN != 15) {
43 printk("FATAL: input pin set in DTS %d != %d\n", PIN_IN, 15);
44 k_panic();
45 }
46
47 if (PIN_OUT != 14) {
48 printk("FATAL: output pin set in DTS %d != %d\n", PIN_OUT, 14);
49 k_panic();
50 }
51
52 /* Configure pin RGMII2_RD2 as GPIO5_IO14. */
53 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2 =
54 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_MUX_MODE(5);
55 /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
56 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2 =
57 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PUE_MASK |
58 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_PKE_MASK |
59 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_SPEED(2) |
60 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_DSE(6);
61
62 /* Configure pin RGMII2_RD3 as GPIO5_IO15. */
63 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3 =
64 IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_MUX_MODE(5);
65 /* Select pull enabled, speed 100 MHz, drive strength 43 ohm */
66 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3 =
67 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PUE_MASK |
68 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_PKE_MASK |
69 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_SPEED(2) |
70 IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_DSE(6);
71 #elif defined(CONFIG_BOARD_MIMXRT1050_EVK)
72 IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0);
73 IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23, 0);
74
75 IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22,
76 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
77 IOMUXC_SW_PAD_CTL_PAD_HYS_MASK |
78 IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
79 IOMUXC_SW_PAD_CTL_PAD_DSE(6));
80
81 IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_07_GPIO1_IO23,
82 IOMUXC_SW_PAD_CTL_PAD_PKE_MASK |
83 IOMUXC_SW_PAD_CTL_PAD_SPEED(2) |
84 IOMUXC_SW_PAD_CTL_PAD_DSE(6));
85 #elif defined(CONFIG_GPIO_EMUL)
86 extern struct gpio_callback gpio_emul_callback;
87 const struct device *const dev = DEVICE_DT_GET(DEV);
88
89 zassert_true(device_is_ready(dev), "GPIO dev is not ready");
90 int rc = gpio_add_callback(dev, &gpio_emul_callback);
91 __ASSERT(rc == 0, "gpio_add_callback() failed: %d", rc);
92 #elif defined(CONFIG_BOARD_NRF52_BSIM)
93 static bool done;
94
95 if (!done) {
96 done = true;
97 /* This functions allows to programmatically short-circuit SOC GPIO pins */
98 nrf_gpio_backend_register_short(1, PIN_OUT, 1, PIN_IN);
99 }
100 #endif
101 }
102
gpio_basic_setup(void)103 static void *gpio_basic_setup(void)
104 {
105 board_setup();
106
107 return NULL;
108 }
109
110 /* Test GPIO port configuration */
111 ZTEST_SUITE(gpio_port, NULL, gpio_basic_setup, NULL, NULL, NULL);
112
113 /* Test GPIO callback management */
114 ZTEST_SUITE(gpio_port_cb_mgmt, NULL, gpio_basic_setup, NULL, NULL, NULL);
115
116 /* Test GPIO callbacks */
117 ZTEST_SUITE(gpio_port_cb_vari, NULL, gpio_basic_setup, NULL, NULL, NULL);
118
