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/Zephyr-Core-3.7.0/boards/shields/mikroe_accel13_click/doc/
Dindex.rst3 MikroElektronika ACCEL 13 Click
9 The MikroElektronika ACCEL 13 Click carries the `IIS2DLPC`_ ultra-low
15 .. figure:: accel-13-click.jpg
17 :alt: MikroElektronika ACCEL 13 Click
19 MikroElektronika ACCEL 13 Click (Credit: MikroElektronika)
28 For more information about interfacing the IIS2DLPC and the ACCEL 13 Click,
32 - `ACCEL 13 Click`_
55 .. _ACCEL 13 Click:
56 https://www.mikroe.com/accel-13-click
/Zephyr-Core-3.7.0/samples/modules/cmsis_dsp/moving_average/
Dsample.yaml30 - "Input\\[13\\]: 4 5 6 7 8 9 10 11 12 13 | Output\\[13\\]: 8.50"
31 - "Input\\[14\\]: 5 6 7 8 9 10 11 12 13 14 | Output\\[14\\]: 9.50"
32 - "Input\\[15\\]: 6 7 8 9 10 11 12 13 14 15 | Output\\[15\\]: 10.50"
33 - "Input\\[16\\]: 7 8 9 10 11 12 13 14 15 16 | Output\\[16\\]: 11.50"
34 - "Input\\[17\\]: 8 9 10 11 12 13 14 15 16 17 | Output\\[17\\]: 12.50"
35 - "Input\\[18\\]: 9 10 11 12 13 14 15 16 17 18 | Output\\[18\\]: 13.50"
36 - "Input\\[19\\]: 10 11 12 13 14 15 16 17 18 19 | Output\\[19\\]: 14.50"
37 - "Input\\[20\\]: 11 12 13 14 15 16 17 18 19 20 | Output\\[20\\]: 15.50"
38 - "Input\\[21\\]: 12 13 14 15 16 17 18 19 20 21 | Output\\[21\\]: 16.50"
39 - "Input\\[22\\]: 13 14 15 16 17 18 19 20 21 22 | Output\\[22\\]: 17.50"
/Zephyr-Core-3.7.0/samples/net/dsa/boards/
Dip_k66f.overlay8 local-mac-address = [00 00 12 13 00 10];
12 local-mac-address = [00 00 12 13 00 37];
16 local-mac-address = [00 00 12 13 00 27];
20 local-mac-address = [00 00 12 13 00 17];
/Zephyr-Core-3.7.0/samples/drivers/adc/adc_dt/boards/
Dsaml21_xpro.overlay10 io-channels = <&adc 13>;
29 channel@13 {
30 reg = <13>;
35 zephyr,input-positive = <13>;
/Zephyr-Core-3.7.0/samples/net/gptp/
DREADME.rst102 INFO : GPTP [13:01:14:837] gPTP starting
103 INFO : GPTP [13:01:14:838] priority1 = 248
104 INFO : GPTP [13:01:14:838] announceReceiptTimeout: 3
105 INFO : GPTP [13:01:14:838] syncReceiptTimeout: 3
106 INFO : GPTP [13:01:14:838] LINKSPEED_100MB - PHY delay
108 INFO : GPTP [13:01:14:838] LINKSPEED_1G - PHY delay
110 INFO : GPTP [13:01:14:838] neighborPropDelayThresh: 10000
111 INFO : GPTP [13:01:14:838] syncReceiptThreshold: 8
112 ERROR : GPTP [13:01:14:838] Using clock device: /dev/ptp0
113 STATUS : GPTP [13:01:14:838] Starting PDelay
[all …]
/Zephyr-Core-3.7.0/tests/lib/cmsis_dsp/filtering/src/
Dmisc_f16.c92 DEFINE_CORRELATE_TEST(13, 1);
93 DEFINE_CORRELATE_TEST(13, 2);
94 DEFINE_CORRELATE_TEST(13, 3);
95 DEFINE_CORRELATE_TEST(13, 8);
96 DEFINE_CORRELATE_TEST(13, 11);
172 DEFINE_CONV_TEST(13, 1);
173 DEFINE_CONV_TEST(13, 2);
174 DEFINE_CONV_TEST(13, 3);
175 DEFINE_CONV_TEST(13, 8);
176 DEFINE_CONV_TEST(13, 11);
Dmisc_f32.c100 DEFINE_CORRELATE_TEST(13, 1);
101 DEFINE_CORRELATE_TEST(13, 2);
102 DEFINE_CORRELATE_TEST(13, 3);
103 DEFINE_CORRELATE_TEST(13, 8);
104 DEFINE_CORRELATE_TEST(13, 11);
175 DEFINE_CONV_TEST(13, 1);
176 DEFINE_CONV_TEST(13, 2);
177 DEFINE_CONV_TEST(13, 3);
178 DEFINE_CONV_TEST(13, 8);
179 DEFINE_CONV_TEST(13, 11);
/Zephyr-Core-3.7.0/include/zephyr/dt-bindings/pinctrl/renesas/
Dpinctrl-r8a77961.h27 #define PIN_D13 RCAR_GP_PIN(0, 13)
43 #define PIN_A13 RCAR_GP_PIN(1, 13)
72 #define PIN_AVB_AVTP_MATCH_A RCAR_GP_PIN(2, 13)
87 #define PIN_SD0_WP RCAR_GP_PIN(3, 13)
103 #define PIN_SD3_DATA4 RCAR_GP_PIN(4, 13)
121 #define PIN_HRX0 RCAR_GP_PIN(5, 13)
147 #define PIN_SSI_SDAT_A5 RCAR_GP_PIN(6, 13)
182 #define PIN_AVB_TXC RCAR_NOGP_PIN(13)
699 #define FUNC_TX2_A IPSR(13, 0, 0)
700 #define FUNC_SD2_CD_B IPSR(13, 0, 3)
[all …]
Dpinctrl-r8a77951.h26 #define PIN_D13 RCAR_GP_PIN(0, 13)
42 #define PIN_A13 RCAR_GP_PIN(1, 13)
71 #define PIN_AVB_AVTP_MATCH_A RCAR_GP_PIN(2, 13)
86 #define PIN_SD0_WP RCAR_GP_PIN(3, 13)
102 #define PIN_SD3_DATA4 RCAR_GP_PIN(4, 13)
120 #define PIN_HRX0 RCAR_GP_PIN(5, 13)
146 #define PIN_SSI_SDAT_A5 RCAR_GP_PIN(6, 13)
181 #define PIN_AVB_TXC RCAR_NOGP_PIN(13)
701 #define FUNC_TX2_A IPSR(13, 0, 0)
702 #define FUNC_SD2_CD_B IPSR(13, 0, 3)
[all …]
/Zephyr-Core-3.7.0/drivers/ipm/
Dipm_nrfx_ipc.h45 IPC_EVENT_BIT(13) | \
65 [13] = BIT(13),
83 [13] = BIT(13),
/Zephyr-Core-3.7.0/boards/st/stm32h7s78_dk/
Darduino_r3_connector.dtsi17 <4 0 &gpiof 13 0>, /* A4 */
24 <11 0 &gpiod 13 0>, /* D5 */
26 <13 0 &gpiof 3 0>, /* D7 */
31 <18 0 &gpioe 13 0>, /* D12 */
/Zephyr-Core-3.7.0/subsys/bluetooth/host/
Daes_ccm.c35 dst[13] = a[13] ^ b[13]; in xor16()
40 /* b field is assumed to have the nonce already present in bytes 1-13 */
99 static int ccm_auth(const uint8_t key[16], uint8_t nonce[13], in ccm_auth() argument
114 memcpy(b + 1, nonce, 13); in ccm_auth()
152 static int ccm_crypt(const uint8_t key[16], const uint8_t nonce[13], in ccm_crypt() argument
167 memcpy(&a_i[1], nonce, 13); in ccm_crypt()
191 int bt_ccm_decrypt(const uint8_t key[16], uint8_t nonce[13], in bt_ccm_decrypt() argument
212 int bt_ccm_encrypt(const uint8_t key[16], uint8_t nonce[13], in bt_ccm_encrypt() argument
219 LOG_DBG("nonce %s", bt_hex(nonce, 13)); in bt_ccm_encrypt()
/Zephyr-Core-3.7.0/boards/ezurio/bl654_usb/
Dbl654_usb-pinctrl.dtsi9 psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
15 psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
/Zephyr-Core-3.7.0/boards/rak/rak5010/
Drak5010_nrf52840-pinctrl.dtsi44 <NRF_PSEL(TWIM_SCL, 0, 13)>;
51 <NRF_PSEL(TWIM_SCL, 0, 13)>;
61 <NRF_PSEL(QSPI_IO2, 1, 13)>,
72 <NRF_PSEL(QSPI_IO2, 1, 13)>,
/Zephyr-Core-3.7.0/soc/intel/apollo_lake/
Dsoc_gpio.h36 #define APL_GPIO_13 13
70 #define APL_GPIO_45 13
104 #define APL_GPIO_SVOD0_CLK 13
120 #define APL_GPIO_200 13
154 #define APL_GPIO_85 13
203 #define APL_GPIO_137 13
237 #define APL_GPIO_SUS_STAT_B 13
254 #define APL_GPIO_165 13
/Zephyr-Core-3.7.0/drivers/sensor/ti/fdc2x1x/
Dfdc2x1x.h66 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_MSK GENMASK(13, 12)
85 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_MSK BIT(13)
86 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_SET(x) (((x) & 0x1) << 13)
87 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_GET(x) (((x) >> 13) & 0x1)
105 #define FDC2X1X_CFG_SLEEP_SET_EN_MSK BIT(13)
106 #define FDC2X1X_CFG_SLEEP_SET_EN_SET(x) (((x) & 0x1) << 13)
107 #define FDC2X1X_CFG_SLEEP_SET_EN_GET(x) (((x) >> 13) & 0x1)
125 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_MSK GENMASK(14, 13)
126 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_SET(x) (((x) & 0x3) << 13)
127 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_GET(x) (((x) >> 13) & 0x3)
/Zephyr-Core-3.7.0/boards/phytec/reel_board/dts/
Dreel_board-pinctrl.dtsi58 psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
70 psels = <NRF_PSEL(PWM_OUT0, 0, 13)>,
82 <NRF_PSEL(SPIM_MOSI, 1, 13)>;
90 <NRF_PSEL(SPIM_MOSI, 1, 13)>;
/Zephyr-Core-3.7.0/subsys/bluetooth/mesh/
Dcrypto.h26 int bt_mesh_ccm_encrypt(const struct bt_mesh_key *key, uint8_t nonce[13], const uint8_t *plaintext,
30 int bt_mesh_ccm_decrypt(const struct bt_mesh_key *key, uint8_t nonce[13], const uint8_t *enc_data,
94 int bt_mesh_prov_nonce(const uint8_t dhkey[32], const uint8_t prov_salt[16], uint8_t nonce[13]);
139 int bt_mesh_prov_decrypt(struct bt_mesh_key *key, uint8_t nonce[13], const uint8_t data[25 + 8],
142 int bt_mesh_prov_encrypt(struct bt_mesh_key *key, uint8_t nonce[13], const uint8_t data[25],
151 int bt_mesh_beacon_decrypt(const struct bt_mesh_key *pbk, const uint8_t random[13],
155 const uint8_t random[13], uint8_t data[5], uint8_t auth[8]);
/Zephyr-Core-3.7.0/tests/drivers/gpio/gpio_basic_api/boards/
Dmec172xevb_assy6906.overlay13 * Connect the JP71 pin 11 and 13 to test the GPIO loopback
16 out-gpios = <MCHP_GPIO_DECODE_157 0>; /* GPIO_157, JP71 Pin 13 */
/Zephyr-Core-3.7.0/samples/boards/nrf/mesh/onoff_level_lighting_vnd_app/src/mesh/
Dpublisher.c95 bt_mesh_model_msg_init(root_models[13].pub->msg, in publish()
97 net_buf_simple_add_le16(root_models[13].pub->msg, LEVEL_U25); in publish()
98 net_buf_simple_add_u8(root_models[13].pub->msg, tid++); in publish()
99 net_buf_simple_add_u8(root_models[13].pub->msg, 0x45); in publish()
100 net_buf_simple_add_u8(root_models[13].pub->msg, 0x28); in publish()
101 err = bt_mesh_model_publish(&root_models[13]); in publish()
161 bt_mesh_model_msg_init(root_models[13].pub->msg, in publish()
163 net_buf_simple_add_le16(root_models[13].pub->msg, LEVEL_U100); in publish()
164 net_buf_simple_add_u8(root_models[13].pub->msg, tid++); in publish()
165 net_buf_simple_add_u8(root_models[13].pub->msg, 0x45); in publish()
[all …]
/Zephyr-Core-3.7.0/boards/u-blox/ubx_evkninab3/
Dubx_evkninab3_nrf52840-pinctrl.dtsi9 psels = <NRF_PSEL(UART_TX, 1, 13)>,
18 psels = <NRF_PSEL(UART_TX, 1, 13)>,
77 psels = <NRF_PSEL(PWM_OUT0, 0, 13)>,
86 psels = <NRF_PSEL(PWM_OUT0, 0, 13)>,
/Zephyr-Core-3.7.0/include/zephyr/net/
Dmii.h60 #define MII_BMCR_SPEED_LSB (1 << 13)
74 #define MII_BMCR_SPEED_MASK (1 << 6 | 1 << 13)
76 #define MII_BMCR_SPEED_10 (0 << 6 | 0 << 13)
78 #define MII_BMCR_SPEED_100 (0 << 6 | 1 << 13)
80 #define MII_BMCR_SPEED_1000 (1 << 6 | 0 << 13)
88 #define MII_BMSR_100BASE_X_HALF (1 << 13)
121 #define MII_ADVERTISE_REMOTE_FAULT (1 << 13)
158 #define MII_ESTAT_1000BASE_T_FULL (1 << 13)
/Zephyr-Core-3.7.0/dts/bindings/display/
Dled-strip-matrix.yaml24 [12][13][14][15]
30 [15][14][13][12]
41 [12][13][14][15]
47 [15][14][13][12]
55 [12][13][14][15]
61 [15][14][13][12]
89 [15][14][13][12] [31][30][29][28]
104 [15][14][13][12]
/Zephyr-Core-3.7.0/samples/sensor/ina219/boards/
Dblackpill_f411ce.overlay18 sadc = <13>;
19 badc = <13>;
/Zephyr-Core-3.7.0/samples/tfm_integration/tfm_secure_partition/dummy_partition/
Ddummy_partition.c21 { {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
22 { {1, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
23 { {2, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
24 { {3, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },
25 { {4, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15} },

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