1/*
2 * Copyright (c) 2022 Nordic Semiconductor ASA
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7&pinctrl {
8	uart0_default: uart0_default {
9		group1 {
10			psels = <NRF_PSEL(UART_TX, 0, 6)>;
11		};
12		group2 {
13			psels = <NRF_PSEL(UART_RX, 0, 8)>;
14			bias-pull-up;
15		};
16	};
17
18	uart0_sleep: uart0_sleep {
19		group1 {
20			psels = <NRF_PSEL(UART_TX, 0, 6)>,
21				<NRF_PSEL(UART_RX, 0, 8)>;
22			low-power-enable;
23		};
24	};
25
26	uart1_default: uart1_default {
27		group1 {
28			psels = <NRF_PSEL(UART_RX, 1, 1)>,
29				<NRF_PSEL(UART_TX, 1, 2)>;
30		};
31	};
32
33	uart1_sleep: uart1_sleep {
34		group1 {
35			psels = <NRF_PSEL(UART_RX, 1, 1)>,
36				<NRF_PSEL(UART_TX, 1, 2)>;
37			low-power-enable;
38		};
39	};
40
41	i2c0_default: i2c0_default {
42		group1 {
43			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
44				<NRF_PSEL(TWIM_SCL, 0, 27)>;
45		};
46	};
47
48	i2c0_sleep: i2c0_sleep {
49		group1 {
50			psels = <NRF_PSEL(TWIM_SDA, 0, 26)>,
51				<NRF_PSEL(TWIM_SCL, 0, 27)>;
52			low-power-enable;
53		};
54	};
55
56	pwm0_default: pwm0_default {
57		group1 {
58			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>;
59		};
60		group2 {
61			psels = <NRF_PSEL(PWM_OUT1, 0, 11)>,
62				<NRF_PSEL(PWM_OUT2, 0, 12)>,
63				<NRF_PSEL(PWM_OUT3, 1, 9)>;
64			nordic,invert;
65		};
66	};
67
68	pwm0_sleep: pwm0_sleep {
69		group1 {
70			psels = <NRF_PSEL(PWM_OUT0, 0, 13)>,
71				<NRF_PSEL(PWM_OUT1, 0, 11)>,
72				<NRF_PSEL(PWM_OUT2, 0, 12)>,
73				<NRF_PSEL(PWM_OUT3, 1, 9)>;
74			low-power-enable;
75		};
76	};
77
78	spi3_default: spi3_default {
79		group1 {
80			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
81				<NRF_PSEL(SPIM_MISO, 1, 14)>,
82				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
83		};
84	};
85
86	spi3_sleep: spi3_sleep {
87		group1 {
88			psels = <NRF_PSEL(SPIM_SCK, 1, 15)>,
89				<NRF_PSEL(SPIM_MISO, 1, 14)>,
90				<NRF_PSEL(SPIM_MOSI, 1, 13)>;
91			low-power-enable;
92		};
93	};
94
95};
96