1 /* 2 * Copyright (c) 2020 arithmetics.io 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef ZEPHYR_DRIVERS_SENSOR_FDC2X1X_FDC2X1X_H_ 8 #define ZEPHYR_DRIVERS_SENSOR_FDC2X1X_FDC2X1X_H_ 9 10 #include <zephyr/drivers/sensor.h> 11 #include <zephyr/drivers/i2c.h> 12 #include <zephyr/drivers/gpio.h> 13 14 #define PI (3.14159265) 15 16 /* 17 * FDC2X1X registers definition 18 */ 19 #define FDC2X1X_DATA_CH0 0x00 20 #define FDC2X1X_DATA_LSB_CH0 0x01 21 #define FDC2X1X_DATA_CH1 0x02 22 #define FDC2X1X_DATA_LSB_CH1 0x03 23 #define FDC2X1X_DATA_CH2 0x04 24 #define FDC2X1X_DATA_LSB_CH2 0x05 25 #define FDC2X1X_DATA_CH3 0x06 26 #define FDC2X1X_DATA_LSB_CH3 0x07 27 #define FDC2X1X_RCOUNT_CH0 0x08 28 #define FDC2X1X_RCOUNT_CH1 0x09 29 #define FDC2X1X_RCOUNT_CH2 0x0A 30 #define FDC2X1X_RCOUNT_CH3 0x0B 31 #define FDC2X1X_OFFSET_CH0 0x0C 32 #define FDC2X1X_OFFSET_CH1 0x0D 33 #define FDC2X1X_OFFSET_CH2 0x0E 34 #define FDC2X1X_OFFSET_CH3 0x0F 35 #define FDC2X1X_SETTLECOUNT_CH0 0x10 36 #define FDC2X1X_SETTLECOUNT_CH1 0x11 37 #define FDC2X1X_SETTLECOUNT_CH2 0x12 38 #define FDC2X1X_SETTLECOUNT_CH3 0x13 39 #define FDC2X1X_CLOCK_DIVIDERS_CH0 0x14 40 #define FDC2X1X_CLOCK_DIVIDERS_CH1 0x15 41 #define FDC2X1X_CLOCK_DIVIDERS_CH2 0x16 42 #define FDC2X1X_CLOCK_DIVIDERS_CH3 0x17 43 #define FDC2X1X_STATUS 0x18 44 #define FDC2X1X_ERROR_CONFIG 0x19 45 #define FDC2X1X_CONFIG 0x1A 46 #define FDC2X1X_MUX_CONFIG 0x1B 47 #define FDC2X1X_RESET_DEV 0x1C 48 #define FDC2X1X_DRIVE_CURRENT_CH0 0x1E 49 #define FDC2X1X_DRIVE_CURRENT_CH1 0x1F 50 #define FDC2X1X_DRIVE_CURRENT_CH2 0x20 51 #define FDC2X1X_DRIVE_CURRENT_CH3 0x21 52 #define FDC2X1X_MANUFACTURER_ID 0x7E 53 #define FDC2X1X_DEVICE_ID 0x7F 54 55 #define FDC2X1X_MANUFACTURER_ID_VAL 0x5449 56 57 #define FDC2X1X_DEVICE_ID_VAL_28BIT 0x3055 58 #define FDC2X1X_DEVICE_ID_VAL 0x3054 59 60 #define FDC2X1X_READ 0x01u 61 #define FDC2X1X_REG_READ(x) (((x & 0xFF) << 1) | FDC2X1X_READ) 62 #define FDC2X1X_REG_WRITE(x) ((x & 0xFF) << 1) 63 #define FDC2X1X_TO_I2C_REG(x) ((x) >> 1) 64 65 /* CLOCK_DIVIDERS_CHX Field Descriptions */ 66 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_MSK GENMASK(13, 12) 67 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_SET(x) (((x) & 0x3) << 12) 68 #define FDC2X1X_CLK_DIV_CHX_FIN_SEL_GET(x) (((x) >> 12) & 0x3) 69 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_MSK GENMASK(9, 0) 70 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_SET(x) ((x) & 0x1FF) 71 #define FDC2X1X_CLK_DIV_CHX_FREF_DIV_GET(x) (((x) >> 0) & 0x1FF) 72 73 /* STATUS Field Descriptions */ 74 #define FDC2X1X_STATUS_ERR_CHAN(x) (((x) >> 14) & 0x3) 75 #define FDC2X1X_STATUS_ERR_WD(x) (((x) >> 11) & 0x1) 76 #define FDC2X1X_STATUS_ERR_AHW(x) (((x) >> 10) & 0x1) 77 #define FDC2X1X_STATUS_ERR_ALW(x) (((x) >> 9) & 0x1) 78 #define FDC2X1X_STATUS_DRDY(x) (((x) >> 6) & 0x1) 79 #define FDC2X1X_STATUS_CH0_UNREADCONV_RDY(x) (((x) >> 3) & 0x1) 80 #define FDC2X1X_STATUS_CH1_UNREADCONV_RDY(x) (((x) >> 2) & 0x1) 81 #define FDC2X1X_STATUS_CH2_UNREADCONV_RDY(x) (((x) >> 1) & 0x1) 82 #define FDC2X1X_STATUS_CH3_UNREADCONV_RDY(x) (((x) >> 0) & 0x1) 83 84 /* ERROR_CONFIG */ 85 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_MSK BIT(13) 86 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_SET(x) (((x) & 0x1) << 13) 87 #define FDC2X1X_ERROR_CONFIG_WD_ERR2OUT_GET(x) (((x) >> 13) & 0x1) 88 #define FDC2X1X_ERROR_CONFIG_AH_WARN2OUT_MSK BIT(12) 89 #define FDC2X1X_ERROR_CONFIG_AH_WARN2OUT_SET(x) (((x) & 0x1) << 12) 90 #define FDC2X1X_ERROR_CONFIG_AH_WARN2OUT_GET(x) (((x) >> 12) & 0x1) 91 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_MSK BIT(11) 92 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_SET(x) (((x) & 0x1) << 11) 93 #define FDC2X1X_ERROR_CONFIG_AL_WARN2OUT_GET(x) (((x) >> 11) & 0x1) 94 #define FDC2X1X_ERROR_CONFIG_WD_ERR2INT_MSK BIT(5) 95 #define FDC2X1X_ERROR_CONFIG_WD_ERR2INT_SET(x) (((x) & 0x1) << 5) 96 #define FDC2X1X_ERROR_CONFIG_WD_ERR2INT_GET(x) (((x) >> 5) & 0x1) 97 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_MSK BIT(0) 98 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_SET(x) (((x) & 0x1) << 0) 99 #define FDC2X1X_ERROR_CONFIG_DRDY_2INT_GET(x) (((x) >> 0) & 0x1) 100 101 /* CONFIG Field Descriptions */ 102 #define FDC2X1X_CFG_ACTIVE_CHAN_MSK GENMASK(15, 14) 103 #define FDC2X1X_CFG_ACTIVE_CHAN_SET(x) (((x) & 0x3) << 14) 104 #define FDC2X1X_CFG_ACTIVE_CHAN_GET(x) (((x) >> 14) & 0x3) 105 #define FDC2X1X_CFG_SLEEP_SET_EN_MSK BIT(13) 106 #define FDC2X1X_CFG_SLEEP_SET_EN_SET(x) (((x) & 0x1) << 13) 107 #define FDC2X1X_CFG_SLEEP_SET_EN_GET(x) (((x) >> 13) & 0x1) 108 #define FDC2X1X_CFG_SENSOR_ACTIVATE_SEL_MSK BIT(11) 109 #define FDC2X1X_CFG_SENSOR_ACTIVATE_SEL_SET(x) (((x) & 0x1) << 11) 110 #define FDC2X1X_CFG_SENSOR_ACTIVATE_SEL_GET(x) (((x) >> 11) & 0x1) 111 #define FDC2X1X_CFG_REF_CLK_SRC_MSK BIT(9) 112 #define FDC2X1X_CFG_REF_CLK_SRC_SET(x) (((x) & 0x1) << 9) 113 #define FDC2X1X_CFG_REF_CLK_SRC_GET(x) (((x) >> 9) & 0x1) 114 #define FDC2X1X_CFG_INTB_DIS_MSK BIT(7) 115 #define FDC2X1X_CFG_INTB_DIS_SET(x) (((x) & 0x1) << 7) 116 #define FDC2X1X_CFG_INTB_DIS_GET(x) (((x) >> 7) & 0x1) 117 #define FDC2X1X_CFG_HIGH_CURRENT_DRV_MSK BIT(6) 118 #define FDC2X1X_CFG_HIGH_CURRENT_DRV_SET(x) (((x) & 0x1) << 6) 119 #define FDC2X1X_CFG_HIGH_CURRENT_DRV_GET(x) (((x) >> 6) & 0x1) 120 121 /* MUX_CONFIG Field Descriptions */ 122 #define FDC2X1X_MUX_CFG_AUTOSCAN_EN_MSK BIT(15) 123 #define FDC2X1X_MUX_CFG_AUTOSCAN_EN_SET(x) (((x) & 0x1) << 15) 124 #define FDC2X1X_MUX_CFG_AUTOSCAN_EN_GET(x) (((x) >> 15) & 0x1) 125 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_MSK GENMASK(14, 13) 126 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_SET(x) (((x) & 0x3) << 13) 127 #define FDC2X1X_MUX_CFG_RR_SEQUENCE_GET(x) (((x) >> 13) & 0x3) 128 #define FDC2X1X_MUX_CFG_DEGLITCH_MSK GENMASK(2, 0) 129 #define FDC2X1X_MUX_CFG_DEGLITCH_SET(x) ((x) & 0x7) 130 #define FDC2X1X_MUX_CFG_DEGLITCH_GET(x) (((x) >> 0) & 0x7) 131 132 /* RESET_DEV Field Descriptions */ 133 #define FDC2X1X_RESET_DEV_MSK BIT(15) 134 #define FDC2X1X_RESET_DEV_SET(x) (((x) & 0x1) << 15) 135 #define FDC2X1X_RESET_DEV_OUTPUT_GAIN_MSK GENMASK(10, 9) 136 #define FDC2X1X_RESET_DEV_OUTPUT_GAIN_SET(x) (((x) & 0x3) << 9) 137 #define FDC2X1X_RESET_DEV_OUTPUT_GAIN_GET(x) (((x) >> 9) & 0x3) 138 139 /* DRIVE_CURRENT_CHX Field Descriptions */ 140 #define FDC2X1X_DRV_CURRENT_CHX_IDRIVE_MSK GENMASK(15, 11) 141 #define FDC2X1X_DRV_CURRENT_CHX_IDRIVE_SET(x) (((x) & 0x1F) << 11) 142 #define FDC2X1X_DRV_CURRENT_CHX_IDRIVE_GET(x) (((x) >> 11) & 0x1F) 143 144 enum fdc2x1x_op_mode { 145 FDC2X1X_ACTIVE_MODE, 146 FDC2X1X_SLEEP_MODE 147 }; 148 149 struct fdc2x1x_data { 150 bool fdc221x; 151 152 #ifdef CONFIG_FDC2X1X_TRIGGER 153 struct gpio_callback gpio_cb; 154 uint16_t int_config; 155 156 struct k_mutex trigger_mutex; 157 sensor_trigger_handler_t drdy_handler; 158 const struct sensor_trigger *drdy_trigger; 159 const struct device *dev; 160 161 #ifdef CONFIG_FDC2X1X_TRIGGER_OWN_THREAD 162 K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_FDC2X1X_THREAD_STACK_SIZE); 163 struct k_sem gpio_sem; 164 struct k_thread thread; 165 #elif CONFIG_FDC2X1X_TRIGGER_GLOBAL_THREAD 166 struct k_work work; 167 #endif 168 #endif /* CONFIG_FDC2X1X_TRIGGER */ 169 170 uint32_t *channel_buf; 171 }; 172 173 struct fdc2x1x_chx_config { 174 uint16_t rcount; 175 uint16_t offset; 176 uint16_t settle_count; 177 uint16_t fref_divider; 178 uint8_t idrive; 179 uint8_t fin_sel; 180 uint8_t inductance; 181 }; 182 183 struct fdc2x1x_config { 184 struct i2c_dt_spec i2c; 185 struct gpio_dt_spec sd_gpio; 186 187 #ifdef CONFIG_FDC2X1X_TRIGGER 188 struct gpio_dt_spec intb_gpio; 189 #endif 190 191 bool fdc2x14; 192 uint8_t num_channels; 193 194 /* Device Settings */ 195 bool autoscan_en; 196 uint8_t rr_sequence; 197 uint8_t active_channel; 198 uint8_t output_gain; 199 uint8_t deglitch; 200 uint8_t sensor_activate_sel; 201 uint8_t clk_src; 202 uint8_t current_drv; 203 uint16_t fref; 204 205 /* Channel Settings */ 206 const struct fdc2x1x_chx_config *ch_cfg; 207 }; 208 209 int fdc2x1x_set_interrupt_pin(const struct device *dev, bool enable); 210 int fdc2x1x_get_status(const struct device *dev, uint16_t *status); 211 int fdc2x1x_reg_write_mask(const struct device *dev, uint8_t reg_addr, 212 uint16_t mask, uint16_t data); 213 214 #ifdef CONFIG_FDC2X1X_TRIGGER 215 216 int fdc2x1x_trigger_set(const struct device *dev, 217 const struct sensor_trigger *trig, 218 sensor_trigger_handler_t handler); 219 220 int fdc2x1x_init_interrupt(const struct device *dev); 221 #endif /* CONFIG_FDC2X1X_TRIGGER */ 222 223 #endif /* ZEPHYR_DRIVERS_SENSOR_FDC2X1X_FDC2X1X_H_ */ 224
