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/Zephyr-latest/boards/shields/waveshare_epaper/
Dwaveshare_epaper_gdey0213b74.overlay27 height = <122>;
/Zephyr-latest/doc/connectivity/networking/conn_mgr/figures/
Dintegration_diagram_simplified.drawio14 <mxGeometry x="271" y="-122" width="116" height="348" as="geometry" />
28 …fillColor=#CCE5FF;elbow=vertical;" parent="1" source="Db8zi3n4dXzB52SZQf6J-122" target="Db8zi3n4dX…
31 …<mxCell id="Db8zi3n4dXzB52SZQf6J-122" value="Connectivity Control" style="rounded=0;whiteSpace=wra…
34 …imeter=0;" parent="1" source="Db8zi3n4dXzB52SZQf6J-124" target="Db8zi3n4dXzB52SZQf6J-122" edge="1">
85 …rimeter=0;" parent="1" source="Db8zi3n4dXzB52SZQf6J-11" target="Db8zi3n4dXzB52SZQf6J-122" edge="1">
Dintegration_diagram_detailed.drawio17 <mxGeometry x="285" y="-122" width="116" height="559" as="geometry" />
141 …<mxCell id="Db8zi3n4dXzB52SZQf6J-122" value="Connectivity Control" style="rounded=0;whiteSpace=wra…
144 …vertical;" parent="1" source="Db8zi3n4dXzB52SZQf6J-124" target="Db8zi3n4dXzB52SZQf6J-122" edge="1">
150 …xitDx=0;exitDy=0;exitPerimeter=0;" parent="1" source="Db8zi3n4dXzB52SZQf6J-122" target="Db8zi3n4dX…
187 …;exitDy=0;" parent="1" source="Db8zi3n4dXzB52SZQf6J-11" target="Db8zi3n4dXzB52SZQf6J-122" edge="1">
/Zephyr-latest/samples/sensor/vcnl4040/
DREADME.rst54 Proximity: 122
/Zephyr-latest/dts/bindings/clock/
Dst,stm32u0-pll-clock.yaml20 The PLL output frequency must not exceed 122 MHz.
/Zephyr-latest/include/zephyr/dt-bindings/pinctrl/
Desp32c6-gpio-sigmap.h249 #define ESP_SPID_IN 122
250 #define ESP_SPID_OUT 122
Desp32c3-gpio-sigmap.h172 #define ESP_NBT_BLE 122
Desp32s3-gpio-sigmap.h222 #define ESP_SUBSPIHD_IN 122
223 #define ESP_SUBSPIHD_OUT 122
/Zephyr-latest/tests/kernel/timer/timer_behavior/
DKconfig37 # ~122 us (see SYS_CLOCK_TICKS_PER_SEC configuration above) and one tick
/Zephyr-latest/boards/particle/nrf52_blenano2/
Dnrf52_blenano2.dts91 * 0x0007ffff (sectors 122-127) is reserved for use
/Zephyr-latest/boards/phytec/reel_board/
Dreel_board.dts63 height = <122>;
Dreel_board_nrf52840_2.overlay44 height = <122>;
/Zephyr-latest/include/zephyr/dt-bindings/gpio/
Dst-morpho-header.h138 #define ST_MORPHO_R_51 122
/Zephyr-latest/tests/lib/cmsis_nn/src/
Dmain.c126 82, 120, -97, -44, -118, 73, 4, -84, -53, -122, -15, 77, 83, 43, 37,
132 125, 17, 6, -4, 46, 119, 113, -116, -125, 80, -57, 122, 75, 119, -117,
134 28, -100, 86, -75, 117, -31, -115, -86, -122, 121, -96, -118, 32, 111, 25,
135 -90, -8, 110, 37, 35, 124, -123, 94, -122, -114, 37, 85, -36, 53, -40,
546 -122, 19, 76, 74, -80, 12, -22, -17, 10, -28, 55, 109, 2, -107,
557 -123, -109, -59, -87, -69, 121, -128, -95, -70, 2, 81, -119, 84, -122};
/Zephyr-latest/boards/ruuvi/ruuvitag/
Druuvi_ruuvitag.dts132 * 0x0007ffff (sectors 122-127) is reserved for use
/Zephyr-latest/samples/sensor/vcnl4040/src/
Dmain.c103 attr.val1 = 122; in test_trigger_mode()
/Zephyr-latest/boards/96boards/nitrogen/
D96b_nitrogen.dts124 * 0x0007ffff (sectors 122-127) is reserved for use
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dnxp_s32k344_clock.h130 #define NXP_S32_QSPI0_RAM_CLK 122U
Dimx95_clock.h175 #define IMX95_CLK_XSPISLVROOT (IMX95_CCM_NUM_CLK_SRC + 122)
/Zephyr-latest/include/zephyr/dt-bindings/interrupt-controller/
Dite-intc.h113 #define IT8XXX2_IRQ_WU117 122
/Zephyr-latest/tests/drivers/gnss/gnss_parse/src/
Dmain.c29 {.str = "122", .base = 16, .value = 290},
/Zephyr-latest/dts/arm/broadcom/
Dvalkyrie-irq.h126 #define PAXB1_MSIX_INTR8 122
/Zephyr-latest/drivers/net/
Dnsos_errno.h79 #define NSOS_MID_EMSGSIZE 122 /**< Message size */
/Zephyr-latest/soc/brcm/bcmvk/valkyrie/
Dsoc.h151 M7_PAXB1_MSIX_INTR8 = 122,
/Zephyr-latest/boards/nordic/thingy52/
Dthingy52_nrf52832.dts216 * 0x0007ffff (sectors 122-127) is reserved for use

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